async_reset

ABEL Reserved Word: async_reset

Purpose

In symbolic state descriptions, the sync_reset and async_reset statements specify synchronous or asynchronous state machine reset logic in terms of symbolic states.

Syntax

SYNC_RESET symbolic_state_id : input_expression ;
ASYNC_RESET symbolic_state_id : input_expression ;

Where symbolic_state_id is an identifier used for reference to a symbolic state and input_expression is any valid expression.

Examples

ASYNC_RESET Start : Reset ;
SYNC_RESET Start : Reset ;


bus

ABEL Reserved Word: bus

This reserved word is not supported for Xilinx designs.


case

ABEL Reserved Word: case

Purpose

The case statement is used under the state_diagram section to indicate the transitions of a state machine when there are multiple possible conditions that affect the state transitions.

You can nest Case statements with if-then-else, goto, and other Case statements, and you can use equation blocks.

Syntax

CASE [ expression : state_exp; ]
[ expression : state_exp; ]
[ expression : state_exp; ]
:
ENDCASE ;

Example

case a == 0 : 1 ;
a == 1 : 2 ;
a == 2 : 3 ;
a == 3 : 0 ;
endcase ;


declarations

ABEL Reserved Word: declarations

Purpose

A declaration is any valid declaration given after the declarations reserved word. Declarations can be declared in any part of the ABEL-HDL source file.

Syntax

DECLARATIONS
declarations

Example

module andor
A,B pin 1,2; "declarations reserved word implied
Out1 pin 15 istype 'com';

Equations
Out1 = A & B;

Declarations "declarations reserved word required
C,D,E,F pin 3,4,5,6;
Out2 pin 16 istype 'com';
Temp1 = C & D;
Temp2 = E & F;

Equations
Out2 = Temp1 # Temp2;

end;


device

ABEL Reserved Word: device

Purpose

The device declaration is not used in Xilinx CPLD designs. The device declaration may be found in existing ABEL modules originally targeted for another PLD. If present, the device declaration should be removed before targeting a Xilinx CPLD.

The device declaration is used with other PLDs to associate the device name used in a module with an actual programmable logic device on which designs are implemented.

Syntax

device_id DEVICE real_device ;

Where device_id is an identifier used for the programmer to load filenames and real_device is a string describing the architecture name of the real device represented by device_id. Only supported devices can be specified.


else

ABEL Reserved Word: else

Used in if-then-else or when-then-else statements.


enable

ABEL Reserved Word: enable

This reserved word is not supported for Xilinx designs.


end

ABEL Reserved Word: end

Purpose

The end statement is paired with the module statement.

See the help section on module for more information.

Syntax

END [module_name]

Example

end source


equations

ABEL Reserved Word: equations

Purpose

The equations statement defines the beginning of a group of equations associated with a device. Equations specify logic functions with Boolean algebra. An ending semicolon is required after each equation.

Use when-then-else for conditional expressions in equations. if-then-else is used only in state_diagram descriptions.

Note The := and ?:= assignment operators are used only when writing pin-to-pin registered equations. Use the = and ?= assignment operators for registered equations using detailed dot extensions.

Syntax

EQUATIONS
element [?]:= condition ;
element [?]= condition ;

Example

equations
A = B & C # A ;
[W,Y] = 3 ;
!F = B == C ;
output.D = in1 # in2 ;


external

ABEL Reserved Word: external

This reserved word is not supported for Xilinx designs.


flag

ABEL Reserved Word: flag

This reserved word is not supported for Xilinx designs.


functional_block

ABEL Reserved Word: functional_block

Purpose

Use a functional_block declaration in a top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the top-level source. You must declare sources with an interface declaration before you instantiate them with a functional_block statement.

Note: The output of an equation must always be on the left side of the equation.

Note: When a source is instanced by a top-level module, any signal attributes (either explicit or implicit) are inherited by the top-level module signals. Therefore, you do not need to specify istypes in top-level sources for instantiated signals.

Syntax

DECLARATIONS
instance_name FUNCTIONAL_BLOCK module_name
EQUATIONS
instance_name.port_name = signal_name; :

Example

module counter;
cnt4 interface (ce, ar, clk -> [q0..q3]); "cnt4's top-level interface declaration. CNT0..CNT3 functional_block cnt4; "Four instances of cnt4

Clk, AR, CE pin;
Q0..Q3 pin;

equations
CNT0.[clk,ar,ce]=[Clk,AR,CE]; "Connecting to Clk, AR, and CE inputs.
[Q0..Q3] = CNT0.[q0..q3] ; "Connecting to Q0..Q3 outputs.
end

Note: Note that the above file instantiates four instances of CNT4, but only one (CNT0) is wired.

Creating Multiple Instances

You can use the range operator (..) to instantiate multiple instance names of the source. For example,

CNT0..CNT3 functional_block
cnt4 ;

Note: The above file creates 4 instances of the submodule CNT4.

Mapping Ports to Signals

Signal names are mapped to port names using equations (similar to wiring the signals on a schematic). You need to specify only the signals used in the top-level source if default values have been specified in the lower-level source interface statement. See interface (lower-level source) for more information on setting default values.

To specify the signal wiring, map signal names to the submodule port names with dot extension notation. There are three kinds of wire: input, output, and interconnect.

Input Wire

Connects submodule outputs to top-level source inputs.

instance.port = input

Output Wire

Connects top-level source outputs to lower-level source inputs.

output = instance.port

Interconnect Wire

Connects the outputs of one instance of a submodule to another instance's inputs.

instance0.port = instance1.port

Overriding Default Values

You can override the default values given in a lower-level source's interface statement by specifying default equations in the top-level source. For example, if you have specified a default value of 1 for the signal ce in interface cnt4 but in instance CNT0, you want ce to be 0, you would write:

CNT0.ce = 0 ;

This equation overrides the 1 with a 0. If you override the default values, you may want to re-optimize the post-linked design.

Unused Outputs (No Connects)

If you do not want to use a submodule's outputs, you can specify them as No Connects (NC) by not wiring up the port to a physical pin. For example, to make a 3-bit counter out of a 4-bit counter in the top-level module, you might use the following wiring equations:

q2..q0 pin ; "top-level
signals
Equations
[q2..q0] = CNT_A.[q2..q0]


fuses

ABEL Reserved Word: fuses

This reserved word is not supported for Xilinx designs.


goto

ABEL Reserved Word: goto

Purpose

The goto statement causes an unconditional transition to the state indicated by state_exp. Goto statements can be nested with if-then-else, case, and with statements.

Syntax

GOTO state_exp ;

Where state_exp is an expression identifying the next state, optionally followed by with transition equations.

Examples

GOTO 0 ; "goto state 0
GOTO x+y ; "goto the state
x + y


group

ABEL Reserved Word: group

This reserved word is not supported for Xilinx designs.


if-then-else

ABEL Reserved Word: if-then-else

Purpose

The if-then-else statement is an easy way to describe the progression from one state to another in a state machine. The expression following the if reserved word is evaluated, and if the result is true, the machine goes to the state indicated by the state_exp following the then reserved word. If the result of the expression is false, the machine advances to the state indicated by the else reserved word.

Additional if-then-else statements can be chained to the else clause of an if-then-else statement. Any number of if-then-else statements can be chained, but the final statement must end with a semicolon.

Note: Equation blocks used within a conditional expression, such as if-then-else, result in logic functions that are logically ANDed with the conditional expression that is in effect.

Note: Caution: If-Then-Else is only supported within a state_diagram description. Use when-then-else for equations.

Syntax

IF expression THEN state_exp
[ ELSE state_exp ] ;

Chained If_Then_Else Syntax

IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE state_expression ;

Where expression is any valid expression and state_exp is an expression identifying the next state, optionally followed by with transition equations.

Example

If A==B then 2 ; "if A equals B goto state 2
if x-y then j else k; "if x-y is not 0 goto j, else goto k
if A then b*c; "if A is true (non-zero) goto state b*c

Chained If-Then-Else Example

if a then 1
else
if b then 2
else
if c then 3
else 0 ;


interface

ABEL Reserved Word: interface

interface (top level)

Purpose

The interface reserved word declares lower-level modules that are used in the current source and defines the order and default values of their ports (signals). This declaration is used in conjunction with a functional_block declaration for each instantiation of the lower-level module.

If the lower-level module uses the interface reserved word to declare signals, the top-level source interface statement must exactly match the signal listing.

Note Interface declarations cannot contain dot extensions. If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source. All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined. No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note When you instantiate a lower-level source in a top-level source, any signal attributes (either explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals. Do not specify istypes for instantiated signals.

Syntax

module_name INTERFACE (input/set[=value]-> output/set :> bidir/set);

Where module_name is the name of the lower-level module being declared; and input/set[=value] -> output/set :> bidir/set is a list of signals in the lower-level module.

Signal names are separated with commas. Use -> and :> to indicate the direction of each port of a functional block.

value is an optional default value for an input that overrides defaults in the lower-level module.

Example

module top;
cnt4 interface (ce,ar,clk -> [q3..q0])

Map port names to signal names with equations. See functional_block.

interface (lower-level)

Purpose

The interface declaration is optional for lower-level modules. Use the interface declaration in lower-level modules to assign a default port list and input values for the module when instantiated in top-level ABEL-HDL sources. If you use the interface statement in an instantiated module, you must declare the signals and sets in the top-level source in the same order and grouping as given in the interface statement in the lower-level module.

Declaring signals in the lower-level module, although optional, does allow the compiler to check for signal declaration mismatches and therefore reduces the possibility of wiring errors.

Syntax

MODULE module_name
INTERFACE (input/set[=value] -> output/set
[:> bidir/set]);

Where module_name is the standard module statement for the ABEL-HDL source and signal/set defines signals or sets in the lower-level module used as ports to top-level modules.

Use -> and :> to indicate the direction of each port of a functional block; and use commas to separate groups of signals

value is the default value for the port for input signals only. Default values do not apply to output and bidirectional signals.

Example

The following interface statement declares inputs ce, ar, and clk, (giving default values for two of them) and outputs q3 through q0.

module cnt4 interface (ce=1,ar=1,clk ->
[q3..q0]) ;

Specifying default values allows you to instantiate cnt4 without declaring the ce and ar inputs in the top-level source. If you do not declare these inputs, they are replaced with the constants 1 and 0, respectively. Since these constants may affect the optimization, you may need to re-optimize the lower-level source with the constants.

Note Supported default values are 1, 0, or X (don't care). You can give default values for a set with a positive integer, and each digit of the integer's binary form supplies the default value for the corresponding signal in the set.

Declared Signals

Declared signals can be a list of lower-level pins, sets or a combination of both. The following constraints apply to the different signal types:

Signal Type Constraints

Input Default values must be binary if applied to an individual bit, or any positive integer applied to a set. All inputs must be listed.

Output Unlisted outputs are interpreted as No connects (NC). Unlisted, fed-back outputs are interpreted as nodes in the top-level source following the naming convention: instance_name/node_name

Bidirectional Listing bidirectional signals are optional, except for those with output enable (OE). If you specify bidirectional signals, the compiler checks for invalid wire connections.

Note Interface declarations cannot contain dot extensions. If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source. All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined. No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note When you instantiate a lower-level source in a top-level source, any signal attributes (explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals.

Caution! Do not specify istypes for instantiated signals.

Unlisted Signals

If you do not list some signals of the lower-level module in the interface statement, the following rules apply:

Unlisted Pins Are: The Compiler Interprets Them As:

  • Inputs or Bidirectionals with OE Errors

  • Outputs No Connects (NC), and they can be removed

  • Feedback outputs nodes in the top-level source, following the naming convention: instance_name/node_name


istype

ABEL Reserved Word: istype

Purpose

The istype statement defines attributes (characteristics) of signals (pins and nodes). You should use signal attributes to remove ambiguities in architecture-independent designs. Even when you have specified a device, using attributes ensures that the design operates consistently if the device is changed later.

You can combine a pin or node declaration with an istype statement in a single declaration. Supported attributes are listed below.

Syntax

signals [PIN | NODE] numbers ISTYPE 'attr';

Where signal is a pin or node identifier, numbers are optional pin or node numbers and attr is a string that specifies attributes for the signals, separated by commas.

Example

F0, A pin istype 'invert, reg' ;

This declaration statement defines F0 and A as inverted D-type flip-flops. The following signal declarations are all supported:

q3,q2,q1,q0 NODE ISTYPE 'reg_SR';
Clk,a,b,c PIN 1,2,3,4;
reset PIN;
reset ISTYPE 'com';
Output PIN 15 ISTYPE 'reg,invert';


library

ABEL Reserved Word: library

Purpose

The library statement causes the contents of the indicated file to be inserted in the ABEL source file. The insertion begins at the point where the library statement is located. The file extension of '.inc' is appended to the name specified, and the resulting file name is searched for. If no file is found, ABEL will attempt to find the file in the abel5lib.inc library file.

Syntax

LIBRARY 'name'

Where name is a string that specifies the name of the file, excluding the file extension.


macro

ABEL Reserved Word: macro

Purpose

The macro declaration statement defines a macro. You can use macros to include ABEL code in a source file without typing or copying the code everywhere you need it. A macro is defined once in the declarations section of a module and then used anywhere within the module as frequently as needed. Macros can be used only within the module in which they are declared.

Syntax

macro_id MACRO [ ( dummy_arg[,dummy_arg]...) ] {block} ;

Where macro_id is an identifier naming the macro; dummy_arg is a dummy argument, and block is a block.

Example

The dummy arguments used in the declaration of the macro allow different actual arguments to be used in the macro each time it is invoked in the module. Within the macro, dummy arguments are preceded by a "?" to indicate that an actual argument will be substituted for the dummy by the ABEL compiler.

D = NAND3 (Clock,Hello,Busy) ;

brings the text in the block associated with NAND3 into the code, with Clock substituted for ?A, Hello for ?B, and Busy for ?C. This results in

D = ! ( Clock & Hello & Busy ) ;

which is the three input NAND.


module

ABEL Reserved Word: module

Purpose

The module statement defines the beginning of a module and must be paired with an end statement that defines the module's end.

Syntax

MODULE modname [ ( dummy_arg
[,dummy_arg] ... ) ]
modname - A valid identifier naming the module.
dummy_arg - A dummy argument.


node

ABEL Reserved Word: node

Purpose

The node reserved word is used to declare those signals that may be assigned to buried nodes within a device.

Syntax

[!]node_id[,[!]node_id...] NODE [node#s...][ISTYPE 'attr'];

Where node_id is an identifier used for reference to a node in a logic design, node #s are the node number on the real device, and attr is a string that specifies node attributes for devices with programmable nodes.

Example

The node attribute string, Istype 'attr', specifies node attributes. The node declaration,

B NODE istype 'reg' ;

specifies that node B is a buried flip-flop.

a0..a3 node 22..25;

Assigns a0, a1, a2, and a3 to nodes 22, 23, 24, and 25, respectively.


options

ABEL Reserved Word: options

This reserved word is not supported for Xilinx designs.


partition

ABEL Reserved Word: partition

This reserved word is not supported for Xilinx designs.


pin

ABEL Reserved Word: pin

Purpose

The pin reserved word is used to declare those input and output signals that must eventually be available on a device I/O pin. You should also specify pin attributes for all pins used as outputs.

When lists of pin_ids and pin_names are used in one pin declaration statement, there is a one-to-one correspondence between the identifiers and numbers given. If you declare pin names, you must include names for each identifier listed in the statement.

For CSP and BGA type packages with alphanumeric row-column pin names, enclose each pin name in single-quotes. For example:

a pin 'B2' istype 'reg';

Syntax

[!]pin_id[,[!]pin_id...] PIN
[pin_name[,pin_name]] [ISTYPE 'attr'];

Where pin_id is an identifier used to refer to a pin signal throughout a module, pin_name is the pin number or name on the real device, and attr is a string that specifies pin attributes for devices with programmable pins.

Example

!Clock, Reset, S1 PIN 12,15,3;

This pin declaration assigns the pin id Clock to pin number 12;
Reset to pin #15; and S1 to pin #3.

The use of the "!' operator in pin declarations indicates that the pin is active-low and will be automatically negated when processed by the language processor.

Errors

The following are pin assignment errors that cause errors in ABEL:

Assigning the same pin number to two signals (A1, A0 pin 17,17;).


place

ABEL Reserved Word: place

This reserved word is not supported for Xilinx designs.


place_input

ABEL Reserved Word: place_input

This reserved word is not supported for Xilinx designs.


property

ABEL Reserved Word: property

Purpose

The property declaration statement allows you to pass supported property information to the CPLD Fitter. The string contains the property information and the names of the design signals to which the properties apply. Property information is applied to the corresponding design elements in the EDIF netlist.

Syntax

xilinx PROPERTY 'string' ;


signal

ABEL Reserved Word: signal

This reserved word is not supported for Xilinx designs.


state

ABEL Reserved Word: state

Used As a Declaration

Purpose

The state declaration is made to declare a symbolic state name, and optionally associate it with a state register.

Syntax

state_id [, state_id ...] STATE [IN statereg_id ]

Where state_id is a symbolic state name to be referenced in a symbolic state description, and statereg_id is an identifier for a state register.

If your design includes more than one symbolic state machine, use the in reserved word to associate each state with the corresponding state register. Each state you declare corresponds to one flip-flop in a one-hot state machine.

Used in a State Diagram)

Purpose

The state reserved word and the associated section describes one state of a state diagram. It includes a state value (or symbolic state name), a state transition statement, and optional state output equations.

The specification of a state description requires the use of the state_diagram syntax (which defines the state machine) and the if-then-else, case, goto, and with-endwith statements (which determine the operation of the state machine). Symbolic state machines (machines for which the actual state registers and state values are unspecified) require additional declarations for the symbolic state register and state names.

An ending semicolon is required after each transition statement.

Syntax

[STATE state_exp : [equation]
[equation]
:
:
trans_stmt ; ...]

Where state_exp is an expression, value, or symbolic state name giving the current state, equation is a valid equation that defines the state machine outputs, and trans_stmt can be if-then-else, case, or goto statements, optionally followed by with transition equations.


state_diagram

ABEL Reserved Word: state_diagram

Purpose

The state description describes the operation of a sequential state machine implemented with programmable logic. You can use state descriptions to describe logic as an alternative to Boolean equations or truth tables.

Syntax

STATE_DIAGRAM state_reg
[-> state_out]
STATE state_exp : [equation]
[equation]
:
:
trans_stmt ;]

Where state_reg is an identifier or set of identifiers specifying the signals that determine the current state of the machine, state_out is an identifier or set of identifiers that determine the next state of the machine (for designs with external registers); and where state_exp is an expression giving the current state, equation is a valid equation that defines the state machine outputs, and trans_stmt is an if-then-else statement.

Example

The following is an example of a simple state machine that advances from one state to the next, setting the output to the current state, and then starting over again. Note that the states do not need to be specified in any particular order. Note also that state 2 is identified by an expression rather than by a constant. The state register is composed of the signals a and b.

state_diagram [a,b]
state 3: y = 3 ;
goto 0 ;
state 1: y = 1 ;
goto S2 ;
state 0: y = 0 ;
goto 1 ;
state S2; y = S2 ;
goto 3 ;


state_register

ABEL Reserved Word: state_register

Purpose

For symbolic state diagrams, state_register declares a symbolic state machine name.

Syntax

statereg_id STATE_REGISTER ;

Where statereg_id is an identifier naming the state_register.


sync_reset

ABEL Reserved Word: sync_reset

Purpose

In symbolic state descriptions, the sync_reset and async_reset statements specify synchronous or asynchronous state machine reset logic in terms of symbolic states.

Syntax

SYNC_RESET symbolic_state_id : input_expression ;
ASYNC_RESET symbolic_state_id : input_expression ;

Where symbolic_state_id is an identifier used for reference to a symbolic state and input_expression is any valid expression.

Examples

ASYNC_RESET Start : Reset ;
SYNC_RESET Start : Reset ;


test_vectors

ABEL Reserved Word: test_vectors

Purpose

Test vectors specify the expected functional operation of a logic device by explicitly defining the device outputs as functions of the inputs. Test vectors are used for simulation of an internal model of the device and for functional testing of the programmed device.

Syntax

TEST_VECTORS [note]
(inputs -> outputs )
invalues -> outvalues ;
...

Where note is a string used to describe the test vectors, inputs is an identifier or set of identifiers specifying the names of the input signals to the device, or feedback output signals; and where outputs is an identifier or set of identifiers specifying the output signals from the device invalues is an input value or set of input values, and outvalues is an output value or set of output values resulting from the given inputs.

Examples

Following is a simple test vector table:

TEST_VECTORS
( [A,B] -> [C,D] )
[0,0] -> [1,1] ;
[0,1] -> [1,0] ;
[1,0] -> [0,1] ;
[1,1] -> [0,0] ;

The following test vector table is equivalent to the table specified above because values for sets can be specified with numeric constants.

TEST_VECTORS
( [A,B] -> [C,D] )
0 -> 3 ;
1 -> 2 ;
2 -> 1 ;
3 -> 0 ;

If the signal identifiers in the test vector header were declared as active-low in the declaration section, then constant values specified in the test vectors will be inverted accordingly.


then

ABEL Reserved Word: then

Used in if-then-else or when-then-else statements.


title

ABEL Reserved Word: title

Purpose

The title statement is used to give a module a title that will appear as a header in both the programmer load file and documentation file created by the language processor. The title is specified in the string following the reserved word, title. The string is opened and closed by an apostrophe. The title statement is optional.

Syntax

TITLE 'string'

Example

An example of a title statement that spans three lines and describes the logic design is shown below:

module m6809a
title '6809 memory decode, Jean Designer
Data I/O Corp Redmond WA'


trace

ABEL Reserved Word: trace

Purpose

The trace statement is used to control the display features of the PLASim simulation module. Trace statements can be placed before a test vector section, or embedded within a sequence of test vectors.

Syntax

TRACE (inputs -> outputs) ;

Example

TRACE ( [A,B] -> [C ] );
TEST_VECTORS ( [A,B] -> [C,D] )
0 -> 3 ;
1 -> 2 ;
TRACE ( [A,B] -> [ D] );
2 -> 1 ;
3 -> 0 ;


truth_table

ABEL Reserved Word: truth_table

Purpose

Truth tables specify outputs as functions of different input combinations in a tabular form. Truth tables are another way to describe logic designs with ABEL and may be used in lieu of (or in addition to) equations and state diagrams. A truth table includes a header describing the format of the table and the table.

Syntax

TRUTH_TABLE ( inputs -> outputs )
invalues -> outvalues ;
or
TRUTH_TABLE ( inputs :> reg_outs )
invalues :> reg_outvalues ;
or
TRUTH_TABLE ( inputs :> reg_outs -> outputs )
invalues :> reg_outvalues -> outvalues ;

Where inputs are input signal names to the logic function outputs are output signal names from the logic function and reg_outs are registered (clocked) output signal names.

-> - Indicates the input to output function for combinational outputs.

:> - Indicates the input to output function for registered outputs.


when-then-else

ABEL Reserved Word: when-then-else

Purpose

This statement is used in equations. Equations use the four assignment operators = and ?= (combinational or detailed), and := and ?:= (registered pin-to-pin).

Syntax

[ WHEN condition THEN ] [!] element=expression ;
[ ELSE equation ];
or
[ WHEN condition THEN ] equation ;
[ ELSE equation ];

Where condition is any valid expression, element is an identifier naming a signal or set of signals, or an actual set, to which the value of the expression will be assigned, and expression is any valid expression.

Note: Equation blocks used within a conditional expression such as when-then-else result in logic functions that are logically ANDed with the conditional expression that is in effect.

Note: Caution: When-then-else is only supported in equations. Use if-then-else for state diagrams.

Example

WHEN B THEN A=B;
ELSE A=C;

WHEN (Mode == S_Data) THEN { Out_data := S_in;
S_Valid := 1;
}
ELSE WHEN (Mode == T_Data) THEN { Out_data := T_in;
T_Valid := 1;
}


with

ABEL Reserved Word: with

Purpose

The with statement is used in the state_diagram section. When used in conjunction with the if-then or case statement, it allows output equations to be written in terms of transitions.

Syntax

trans_stmt state_exp WITH { equation
[equation]
}

Where trans_stmt is the if, else, or case statement, state_exp is the next state, and equation is an equation for state machine outputs.

Note: The endwith reserved word is supported for backward compatibility.

Example

state 5 : IF a == 1 then 1
WITH {x := 1 ;
y := 1 ;}
ELSE 2 WITH {x := 0 ;
y := 1 ;}


xor_factors

ABEL Reserved Word: xor_factors

Purpose

The xor_factor section allows you to specify a Boolean expression that is to be factored out of (and XORed with) the sum-of-products reduced equations. This can result in dramatic reductions in the size of the reduced equations. The xor_factor feature is a technique for converting a sum of products (SOP) equation into an exclusive or (xor) equation. The resulting equation contains the sum of product functions that, when exclusively ORed together, have the same function as the original. The xor_factor equation will be divided into the original equation, with factor (or its complement) on one side of the xor and the remainder on the other side.

Syntax

XOR_FACTORS
signal name = xor_factors ;

Example

For the following equations,

!Q16 = A & B & !D
# A & B & !C
# !B & C & D
# !A & C & D

a useful xor_factor would be

XOR_Factors

Q16 = A & B;


Pin-to-Pin Example

This example is a pin-to-pin description of a 2-bit counter with a reset.

module count
q0,q1 pin istype 'reg';
clock pin;
reset pin;
equations
[q1,q0].clk = clock;
[q1,q0] := ([q1.fb,q0.fb] + 1) & !reset;
test vectors ([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 0, 0];
end


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12-to-4 Multiplexer

The following design illustrates the implementation of a 12-bit to 4-output multiplexer using high level equations.

Design Specifications

The following figure shows the block diagram for this design. The multiplexer selects one set of inputs and routes that set to the output. The inputs are a0-a3, b0-b3, and c0-c3. The outputs are y0-y3.

The select lines, s0 and s1, control the decoding that determines which set is routed to the output.

Design Method

The following figure shows the same multiplexer after sets have been used to group the signals. All of the inputs have been grouped into the sets a, b, and c. The outputs are grouped into set y and the select lines are grouped into set select. The grouping of signals into sets takes place in the declaration section of the source file.

When the sets have been declared, specification of the design is made with the following four equations:

when (select == 0) then y = a;
when (select == 1) then y = b;
when (select == 2) then y = c;
when (select == 3) then y = c;

The relational expression (==) produces an expression that evaluates to true or false, depending on the values of s0 and s1.

In the first equation, this expression is then ANDed with the set a which contains the four bits, a0-a3, and could be written as:

y = (select == 0) & a;

Assume select is equal to 0 (s1=0 and s0=0), so a true value is produced. The true is then ANDed with the set a on a bit by bit basis, which in effect sets the product term to a. If select were not equal to 0, the relational expression inside the parentheses would produce a false value. This value, when ANDed with anything would give all 0s.

The other product terms in the equation work in the same manner. Because select takes only one value at a time, only one of the product terms pass the value of an input set along to the output set. The others contribute 0 bits to the OR gates.

Test Vectors

The test vectors for this design are specified in terms of the input, output, and select sets. Note that the values for a set can be specified by decimal numbers and by other sets. The constants H and L, used in the test vectors, were declared as four bit sets containing all ones or all zeros.

12-to-4 Multiplexer Source File

module Mux12T4

title '12 to 4 multiplexer

Xilinx'

mux12t4 device 'P16V8S';

a0..a3 pin 1..4;

b0..b3 pin 5..8;

c0..c3 pin 9..13;

s1,s0 pin 18,19;

y0..3 pin 14..17;

H = [1,1,1,1];

L = [0,0,0,0];

select = .X. ;

y = [y3..y0];

a = [a3..a0];

b = [b3..b0];

c = [c3..c0];

equations

when (select == 0) then y = a;

when (select == 1) then y = b;

when (select == 2) then y = c;

when (select == 3) then y = c;

test_vectors ([select, a, b, c] -> y)

[ 0 , 1, X, X] -> 1; ''select = 0 a->y

[ 0 ,10, H, L] -> 10;

[ 0 , 5, H, L] -> 5;

[ 1 , H, 3, H] -> 3; ''select = 1 b->y

[ 1 ,10, 7, H] -> 7;

[ 1 , L,15, L] -> 15;

[ 2 , L, L, 8] -> 8; ''select = 2 c->y

[ 2 , H, H, 9] -> 9;

[ 2 , L, L, 1] -> 1;

[ 3 , H, H, 0] -> 0; ''select = 3 c->y

[ 3 , L, L, 9] -> 9;

[ 3 , H, L, 0] -> 0;

end


ABEL-HDL Compiler Messages (5000-5499)

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Detailed Descriptions: Designing for Macrocells

One way to understand the difference between pin-to-pin and detailed description methods is to think of detailed descriptions as macrocell specifications. A macrocell is a block of circuitry normally (but not always) associated with a device's I/O pin. The following diagram illustrates a typical macrocell associated with signal Q1:

Detailed descriptions are written for the various input ports (the diagram shows them with dot extension labels) of the macrocell. Note that the macrocell shown features a configurable inversion between the Q output of the flip-flop and the output pin labeled Q1. If this inverter is used (or if a device is selected that features a fixed inversion), then the behavior seen on the Q1 output pin will be inverted from the logic applied to or observed on the various macrocell ports, including the feedback port Q1.q.

Pin-to-pin descriptions, on the other hand, allow you to describe your circuit in terms of the behavior expected on an actual output pin, regardless of the architecture of the underlying macrocell. The following diagram illustrates the pin-to-pin concept:

When pin-to-pin descriptions are written in ABEL-HDL, the "generic macrocell" shown above is synthesized from whatever type of macrocell actually exists in the target device.


Detailed Circuit Descriptions

In contrast to a pin-to-pin description, the same circuit can be specified in a detailed form of design description, as follows:

Q1.CLK = Clock; "Register clocked from input
Q1.D = !Q1.Q # Preset; "D-type f/f used for register

In this form of the design, specifying the D input to a D-type flip-flop and specifying feedback directly from the register restricts the device architectures the design can be implemented in. Furthermore, the equations only describe the inputs to and feedback from the flip-flop, and do not provide any information regarding the configuration of the actual output pin. This means the design will operate quite differently when implemented in a device with inverted outputs (a simple P16R4 PAL device, for example), versus in a device with non-inverting outputs (such as an EP600).

To maintain the correct pin behavior using detailed equations, one additional language element, a 'buffer' (or its complement, 'invert') attribute, is required. The 'buffer' attribute ensures that the final implementation in a device has no inversion between the specified D-type flip-flop and the output pin associated with Q1. For example, add the following to the declarations section:

Q1 pin istype 'buffer';


Detailed Module with Inverted Outputs

module Q1_3
Q1 pin istype 'reg_D,invert';
Clock,Preset pin;

equations
Q1.CLK = Clock;
!Q1.D = Q1.Q # Preset;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

In this version of the module, the existence of an inverter between the output of the D-type flip-flop and the output pin (specified with the 'invert' attribute) has necessitated a change in the equation for Q1.D.

As this example shows, using device independence and pin-to-pin description methods is desirable, since you can describe a circuit completely for any implementation. Using pin-to-pin descriptions and generalized dot extensions (such as .FB, .CLK and .OE) as much as possible allows you to implement your ABEL-HDL module into any one of a particular class of devices. (For example, any device that features enough flip-flops and appropriately configured I/O resources.) However, the need for particular types of device features (such as register preset or reset) might limit your ability to describe your design in a completely architecture-independent way.

If, for example, a built-in register preset feature is used in a simple design, the target architectures are limited. Consider this version of the design:

module Q1_5
Q1 pin istype 'reg,buffer';
Clock,Preset pin;

equations
Q1.CLK = Clock;
Q1.AP = Preset;
Q1 := !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

The equation for Q1 still uses the := assignment operator and .FB for a pin-to-pin description of Q1's behavior, but the use of .AP to describe the reset function requires consideration of different device architectures. The .AP extension, like the .D and .Q extensions, is associated with a flip-flop input, not with a device output pin. If the target device has inverted outputs, the design will not reset properly, so this ambiguous reset behavior is removed by using the 'buffer' attribute, with the result of reducing the number of devices for the design to those that feature non-inverted outputs.

Using .ASET instead of .AP can solve this problem if the fitter being used supports the .ASET dot extension.

The versions 5 and 7 of the design above and below are unambiguous, but each is restricted to certain classes of devices:

module Q1_7
Q1 pin istype 'reg,invert';
Clock,Preset pin;

equations
Q1.CLK = Clock;
Q1.AR = Preset;
Q1 := !Q1.fb ;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end


Examples of Pin-to-pin and Detailed Descriptions

Two equivalent module descriptions, one pin-to-pin and one detailed, are shown below for comparison:

Pin-to-pin Module Description

module Q1_1
Q1 pin istype 'reg';
Clock,Preset pin;

equations
Q1.clk = Clock;
Q1 := !Q1.fb # Preset;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

Detailed Module Description

module Q1_2
Q1 pin istype 'reg_D,buffer';
Clock,Preset pin;

equations
Q1.CLK = Clock;
Q1.D = !Q1.Q # Preset;

test_vectors ([Clock,Preset] -> Q1)
[ .c. , 1 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 0 ] -> 1;
[ .c. , 0 ] -> 0;
[ .c. , 1 ] -> 1;
[ .c. , 1 ] -> 1;
end

The first description can be targeted into virtually any device (if register synthesis and device fitting features are available) while the second one can be targeted only to devices featuring D-type flip-flops and non-inverting outputs.

To implement the second (detailed) module into a device with inverting outputs, the source file would need to be modified as described in Detailed Module with Inverted Outputs :


Hierarchy

Hierarchical CPLD design consists of a top-level source that contains functional blocks that are linked together to create the overall design. The functional blocks that are referenced in the top-level source are placeholders for lower-level logic descriptions, which may in turn contain functional blocks that reference even lower-level logic descriptions. The referencing of a logic description is called "instantiation."

Note A source can be referenced ("instantiated") more than once. Also, a source can be both a lower-level and a top-level source.

Caution: In a hierarchical design, you can't Instantiate a top-level source from a source instantiated below that source.

Using Hierarchy

You use hierarchy declarations in an upper-level ABEL-HDL source to refer to (instantiate) another ABEL-HDL source. To instantiate an ABEL-HDL source file, you need to do the following:

In the lower-level source: (optional)

  1. Identify lower-level I/O Ports (signals) with an Interface statement

In the top-level source:

  2. Declare the lower-level source with an Interface declaration

  3. Instantiate the lower-level source with Functional_block declarations.

Note Hierarchy declarations are not required when instantiating an ABEL-HDL source in a schematic. For instructions on instantiating lower-level source in schematics, refer to your schematic reference.

Instantiating a Lower-level Source in an ABEL-HDL Source

To identify I/O ports in the lower-level source:

You identify an ABEL-HDL source's input and output ports with an Interface declaration directly following the Module statement. The Interface statement defines the ports in the lower-level source that are used by the top-level source.

You must declare all input pins in the ABEL-HDL source as ports. You can optionally specify default values of 0, 1, or don't-care.

You do not have to declare all output pins as ports. Any undeclared outputs become no-connects or redundant nodes. Redundant nodes can later be removed from the designs during post-link optimization.

The following source fragment is an example of a lower-level interface statement.

module lower
interface (a=0, [d3..d0]=7 -> [z0..z7]) ;
title 'example of lower-level interface statement ' ...

This statement identifies input a, d3, d2, d1 and d0 with default values, and outputs z0 through z7. For more information, see Interface (lower-level source).

To specify signal attributes:

Attributes specified for pins in a lower-level source are propagated up to the higher-level source. For example, a lower-level pin with an 'invert' attribute affects the higher-level signal wired to that pin, its preset, reset, preload, and power-up value.

Output Enables (OE)

Connecting a lower-level tristate output to a higher-level pin results in the output enable being specified for the higher-level pin. If another OE is specified for the higher-level pin, it is flagged as an error. Since most tristate outputs are used as bidirectionals, it might be important to keep the lower-level OE.

Buried Nodes

Buried nodes in lower-level sources are handled as follows:

Dangling

Lower-level nodes that do not fanout are propagated to the higher-level source and become dangling nodes. Optimization may remove dangling nodes from the lower-level source.

Combinational

Combinational nodes in a lower-level source become collapsible nodes in the higher-level source.

Registered

Registered nodes are preserved with hierarchical names assigned to them.

Declaring Lower-level Source in the Top-level Source

To declare a lower-level source, you match the lower-level source interface statement with an interface declaration. For example, to declare the lower-level source fragment given above, you would add the following declaration to your upper-level source declarations:

lower interface (a=0, [d3..d0]=7 -> [z0..z7]) ;

You could specify different default values if you want to override the ones given in the instantiated source, but otherwise it must match the lower-level interface statement exactly. See Interface (higher-level source) for more information.

Instantiating Lower-level Source in the Top-level Source

You use a functional_block declaration in an top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the upper-level source. You must declare sources with an interface declaration before you instantiate them.

To instantiate the source declared above, add an interface declaration and signal declarations to your top-level declarations, and port connection equations to your top-level equations as shown in the source fragment below:

DECLARATIONS
low1 FUNCTIONAL_BLOCK lower ;
zed0..zed7 pin ; "upper-level outputs
atop pin ; "upper-level input
d3..d0 pin ; "upper-level inputs

EQUATIONS
low1.a = atop; "wire this source's inputs
low1.[d3..d0] = [d3..d0] ; " to lower-level inputs
[zed0..zed7] = low1.[z0..z7]; "wire this source's outputs to
" lower-level outputs

See Functional_block for more information.


Hierarchy and Retargeting and Fitting

Hierarchy and Retargeting

Redundant Nodes

When you link multiple sources, some redundant nodes may be generated. These nodes usually originate from lower-level outputs that are not being used in the top-level source. For example, when you use a 4-bit counter as a 3-bit counter. The most significant bit of the counter is unused and can be removed from the design to save device resources.

Merging Feedbacks

Linking multiple modules can produce signals with one or more feedback types, such as .FB and .Q. You can tell the optimizer to combine these feedbacks to help the fitting process.

Post-linked Optimization

If your design has a constant tied to an input, you can re-optimize the design. Re-optimizing may further reduce the product terms count. For example, if you have the equation

out = i0 & i1 || !i0 & i2;

and i0 is tied to 1, the resulting equation would be simplified to

out = i1;


Building a Lower-level ABEL-HDL Source

A lower-level ABEL-HDL source is built using an Interface statement that provides information for the top-level source it is referenced. Lower-level ABEL-HDL source need to contain an interface statement, even if the top-level source is a schematic.


Node Collapsing

All combinational nodes by default are collapsible. Nodes to be collapsed (or to be preserved) are flagged through the use of signal attributes in the language. The attributes are:

Istype 'keep' Do not collapse this node.

Istype 'collapse' Collapse this node.

Collapsing provides multi-level optimization for combinational logic. Designs with arithmetic and comparator circuits generally generate large number of product terms which will not fit to any programmable logic device. Node collapsing allows you to describe equations in terms of multi-level combinational nodes, then collapse the nodes into the output until it reaches the product term you specify. The result is an equation that is optimized to fit the device constraints.

Selective Collapsing

In some instances, you may want to keep certain nodes from being collapsed out. For example, some nodes may help in the simulation process. You can specify the nodes you do not want collapsed as Istype 'keep' and the optimizer does not collapse them.


Pin-to-Pin Language Features

You do not need to specify a device in your ABEL-HDL source file. You can also omit pin numbers from signal declarations.

When you do not specify a device or pin numbers, you need to specify pin-to-pin attributes for declared signals, since the ABEL-HDL compiler cannot imply signal attributes from predetermined device attributes. If you do not specify signal attributes or other information (such as the dot extensions, which are described later), your design might not operate consistently if you later transfer it to a different target device.

Device-independence Vs. Architecture-independence

The requirement for signal attributes does not mean that a complex design must always be specified with a particular device in mind. You may still have to understand the differences between, for example, a P22V10 PAL and an EP600 EPLD, but you do not have to specify a particular device when describing your design.

The attributes and dot extensions provided in ABEL-HDL help you refine your design to work consistently when moving from one class of device architecture to another; for example from devices having inverted outputs to those with a particular kind of reset/preset circuitry. The more you refine your design using these language features, the more restrictive your design becomes in terms of the number of device architectures it is appropriate for. However, by using attributes and dot extensions carefully, you can avoid specifying a particular device type, and instead target your design to a more general class of device architectures.

Signal Attributes

Signal attributes remove ambiguities that occur when no specific device architecture is declared. If your design does not use device-related attributes (either implied by a device statement or expressed in an

ISTYPE statement), it may not operate the same way when targeted to different device architectures. See "Pin Declaration," "Node Declaration" and "Istype" in the Chapter "Language Reference."

Signal Dot Extensions

Signal dot extensions, like attributes, are a way you can more precisely describe the behavior of a circuit that may be targeted to different architectures. Dot extensions are applied to signals, and remove the ambiguities in equations.


Resolving Feedback Ambiguities

In the equation above (Q1 := !Q1 # Preset;), there is an ambiguous feedback condition. The signal Q1 appears on the right side of the equation, but there is no indication of whether that fed-back signal should originate at the register, should come directly from the combinational logic that forms the input to the register, or should come from the I/O pin associated with Q1. There is also no indication of what type of register should be used (although register synthesis algorithms could, theoretically, map this equation into virtually any register type). The equation could be more completely specified by writing:

Q1.CLK = Clock; "Register clocked from input
Q1 := !Q1.FB # Preset; "Reg. feedback normalized to pin value

This set of equations describes the circuit completely, and specifies enough information that the circuit will operate identically in virtually any device in which it can be fit. The feedback path is specified to be from the register itself, and the .CLK equation specifies that the memory element is clocked, rather than latched.


Building a Top-level ABEL-HDL Source

To build a top-level ABEL-HDL source, you use the interface and functional_block keywords. The interface keyword is also used in instantiated lower-level files.


Using := for Alternative Flip-flop Types

In ABEL-HDL you can specify a variety of flip-flop types using attributes such as 'reg_D' and 'reg_JK'. However, the use of these attributes does not enforce the use of a specific flip-flop type when a device is selected later, and does not affect the meaning of the := assignment operator. The := assignment can be thought of as a memory operator. The type of register that most closely matches the := operator's behavior is the D-type flip-flop.

The primary use for attributes such as 'reg_D', 'reg_JK' and 'reg_SR' is to control the generation of logic. Specifying one of the 'reg_' attributes (for example, 'reg_D') instructs the ABEL-HDL compiler to generate equations using the.D extension regardless of whether the design was written using .D, := or some other method (for example, state diagrams).

Note You need to also specify 'invert' or 'buffer' whenever using detailed syntax.

Using := for flip-flop types other than D-type is only possible if register synthesis features are available to convert the generated equations into equations appropriate for the alternative flip-flop type specified. Since the use of register synthesis to convert D-type flip-flop stimulus into JK or SR-type stimulus usually results in inefficient circuitry, the use of := for these flip-flop types is discouraged. Instead, you should use the .J and .K extensions (for JK-type flip-flops) or the .S and .R extensions (for SR-type flip-flops) and use a detailed description method (including 'invert' or 'buffer' attributes) to describe designs for these register types.

There is no provision in the language for directly writing pin-to-pin equations for registers other than D-type. State diagrams, however, may be used to describe pin-to-pin behavior for any register type.


Using Symbolic State Machines

Using Symbolic State Descriptions

Symbolic state descriptions describe a state machine without having to specify actual state values. An example of a symbolic state description is shown below.

module SM
a,b,clock pin; " inputs
a_reset,s_reset pin; " reset inputs
x,y pin istype 'com'; " simple outputs

sreg1 state_register;
S0..S3 state;

equations
sreg1.clk = clock;
state_diagram sreg1
state S0:
goto S1 with {x = a & b;
y = 0; };

state S1: if (a & b)
then S2 with {x = 0;
y = 1; };

state S2: x = a & b;
y = 1;
if (a) then S1 else S2;

state S3:
goto S0 with {x = 1;
y = 0; };

async_reset S0: a_reset;

sync_reset S0: s_reset;

end

Symbolic state descriptions use the same syntax as non-symbolic state descriptions; the only difference is the addition of the State_register and State declarations, and the addition of symbolic synchronous and asynchronous reset statements.

Symbolic Reset Statements

In symbolic state descriptions, the Sync_Reset and Async_Reset statements specify synchronous or asynchronous state machine reset logic. For example, to specify that a state machine must asynchronously reset to state Start when the Reset input is true, you write

ASYNC_RESET Start : (Reset) ;

Symbolic Test Vectors

You can also write test vectors to refer to symbolic state values by entering the symbolic state register name in the test vector header (in the output sections), and the symbolic state names in the test vectors as output values.


When to Use Detailed Descriptions

Although the pin-to-pin description is preferable, there are frequently situations in which more detailed descriptions must be used. If you are unsure about which method to use for various parts of your design, examine the design's requirements. If the design uses specific features of a device (such as register preset or unusual flip-flop configurations) then detailed descriptions are probably necessary. If your design is a simple combinational function, or matches the "generic" macrocell in its requirements, then you can probably use simple pin-to-pin descriptions.


State Keyword (in State_diagram)

Syntax

[STATE state_exp : [equation]
[equation]
:
:
trans_stmt ; ...]

state_exp - An expression, value, or symbolic state name giving the current state.

equation - A valid equation that defines the state machine outputs.

trans_stmt - IF-THEN-ELSE, CASE, or GOTO statements, optionally followed by WITH transition equations.

Purpose

The state keyword and the associated section describes one state of a state diagram. It includes a state value (or symbolic state name), a state transition statement, and optional state output equations.

Use

The specification of a state description requires the use of the State_diagram syntax (which defines the state machine) and the If-Then-Else, Case, Goto, and With-endwith statements (which determine the operation of the state machine). Symbolic state machines (machines for which the actual state registers and state values are unspecified) require additional declarations for the symbolic state register and state names.

An ending semicolon is required after each transition statement.


Basic Syntax

Each line in an ABEL-HDL source file must conform to the following syntax rules and restrictions:

  • A line can be up to 150 characters long.

  • Lines are ended by a line feed (hex 0A), by a vertical tab (hex 0B), or by a form feed (hex 0C). Carriage returns in a line are ignored, so common end-of-line sequences, such as carriage return/line feed, are interpreted as line feeds. In most cases, you can end a line by pressing Enter.

  • Keywords, identifiers, and numbers must be separated by at least one space. Exceptions to this rule are lists of identifiers separated by commas, expressions where identifiers or numbers are separated by operators, or where parentheses provide the separation.

  • Neither spaces nor periods can be imbedded in the middle of keywords, numbers, operators, or identifiers. Spaces can appear in strings, comments, blocks, and actual arguments. For example, if the keyword MODULE is entered as MOD ULE, it is interpreted as two identifiers, MOD and ULE. Similarly, if you enter 102 05 (instead of 10205), it is interpreted as two numbers, 102 and 5.

  • Keywords can be uppercase, lowercase or mixed-case.

  • Identifiers (user-supplied names and labels) can be uppercase, lowercase or mixed-case, but are case sensitive: the identifier, output, typed in all lowercase letters, is not the same as the identifier, Output.


Choosing Identifiers

Choosing the right identifiers can make a source file easy to read and understand. The following suggestions can help make your logic descriptions self-explanatory, eliminating the need for extensive documentation.

Choose identifiers that match their function. For example, the pin you're going to use as the carry-in on an adder could be named Carry_In. For a simple OR gate, the two input pins might be given the identifiers IN1 and IN2, and the output might be named OR.

Avoid large numbers of similar identifiers. For example, do not name the outputs of a 16 bit adder: ADDER_OUTPUT_BIT_1 ADDER_OUTPUT_BIT_2 and so on.

Use underscores or mixed-case characters to separate words in your identifier.

THIS_IS_AN_IDENTIFIER
ThisIsAnIdentifier

are much easier to read than

THISISANIDENTIFIER


Identifiers

Identifiers are names that identify the following items:

  • devices

  • device pins or nodes

  • functional blocks

  • sets

  • input or output signals

  • constants

  • macros

  • dummy arguments

All of these items are discussed later in this chapter. The rules and restrictions for identifiers are the same regardless of what the identifier describes.

The rules governing identifiers are listed below:

  • Identifiers can be up to 31 characters. Longer names are flagged as an error.

  • Identifiers must begin with an alphabetic character or with an underscore.

  • Other than the first character, identifiers can contain upper- and lowercase characters, digits, tildes (~), and underscores.

  • You cannot use spaces in an identifier. Use underscores or uppercase letters to separate words.

  • Except for Reserved Identifiers (Keywords), identifiers are case sensitive: uppercase letters and lowercase letters are not the same.

  • You cannot use periods in an identifier, except with a supported dot extension.

Some supported identifiers are listed below:

HELLO
hello
K5input
P_h
This_is_a_long_identifier
AnotherLongIdentifier

Some unsupported identifiers are listed below:

7_ does not begin with a letter or underscore
$4 does not begin with a letter or underscore
HEL.LO contains a period (.LO is not a valid dot extension)
b6 kj contains a space

The last of these identifiers is interpreted as two identifiers, b6 and kj.


Introduction to ABEL-HDL

ABEL-HDL is a hardware description language that supports a variety of behavioral input forms, including high-level equations, state diagrams, and truth tables. The ABEL and Synario versions of the ABEL-HDL compiler (and supporting software) functionally verify ABEL-HDL designs through simulation. The compilers then implement the designs in PLDs or FPGAs. ABEL-HDL designs can also be transferred to other design environments through standard-format design transfer files.

You can enter designs in ABEL-HDL and verify them with little or no concern for the architecture of the target device.

Architecture-independent design descriptions (those that do not include device declarations and pin number declarations) require more comprehensive descriptions than their architecture-specific counterparts. Assumptions that can be made when a particular device is specified are not possible when no device is specified.


Reserved Identifier (Keywords)

The keywords listed below are reserved identifiers. Keywords cannot be used to name devices, pins, nodes, constants, sets, macros, or signals. If a keyword is used in the wrong context, an error is flagged.

async_reset | if | sync_reset
case | in | test_vectors
declarations | interface | then
device | istype | title
else | library | trace
endcase | macro | truth_table
endwith | node | when
equations | options | with
external | pin |
flag (obsolete) | property |
functional_block | state |
fuses | state_diagram |
goto | state_register |


Supported ASCII Characters

All uppercase and lowercase alphabetic characters and most other characters on common keyboards are supported. Valid characters are listed or shown below.

abcdefghijklmnopqrstuvwxyz

ABCDEFGHIJKLMNOPQRSTUVWXYZ

0123456789

<space>

<tab>

! @ # $ ? + & * ( ) -

_ = + [ ] { } ; : ' "

' \ | , < > . / ^ %


ABEL Design Examples

The examples in this section show typical programmable logic applications and serve to illustrate significant ABEL-HDL features. You can use these examples to get started creating your own source files. For complete information on creating a source file, refer to the sections ABEL Language Structure and ABEL Language Syntax .

The examples are divided into the following sections:

Equation Examples

Truth Table Example

State Diagram Example

Blackjack Game Example


ABEL Error Messages

Click on the range that your message number is in.

1000 to 1999 (ABEL-HDL to BLIF Messages)

2000 to 2499 (Equation Optimization Messages)

3507 to 3509 (Latte Messages)

5000 to 5499 (Create Fusemap Messages)

6000 to 6999 (Equation Messages)

14000 to 14999 (BLIF Optimization and Linking Messages)

17000 to 17999 (BLIF to Verilog Messages)

18000 to 18999 (BLIF to NetList Messages)

Application Error -- Call to Undefined Dynalink

Message Types


ABEL-HDL Design Considerations

Hierarchy

Building a Top-level ABEL-HDL Module

Building a Lower-level ABEL-HDL Module

CoolRunner-II Clock Divider (New)

Clock Divider

Feedback

Feedback Normalization

State Diagrams Feedback in Equations

Feedback Specification - .Q and .FB

Feedbacks Specified Without Dot Extensions

Feedback Rules

Pin-to-Pin and Detailed Descriptions

Pin-to-pin vs. Detailed Descriptions for Registered Designs

Symbolic State Machines

Using Symbolic State Machines

Creating Device-Independent Designs

Device Independent ABEL-HDL Sources


ABEL-HDL Reference

General Information about ABEL:

ABEL-HDL Language Structure

ABEL-HDL Language Syntax

ABEL Design Examples

ABEL @Directives

ABEL-HDL Design Considerations

ABEL Error Messages

CPLD-Specific Information:

Istype Attributes

ABEL Dot Extensions for CPLD Designs

ABEL PROPERTY Statements for CPLD Designs


Arguments and Argument Substitution

Variable values can be used in macros, modules and directives. These values are called the arguments of the construct that uses them. In ABEL-HDL, there are two types of arguments: actual and dummy. Their definitions are given here.

Dummy argument - An identifier used to indicate where an actual argument is to be substituted in the macro, module, or directive.

Actual argument - The argument (value) used in the macro, directive or module. The actual argument is substituted for the dummy argument. An actual argument can be any text, including identifiers, numbers, strings, operators, sets, or any other element of ABEL-HDL.

Dummy arguments are specified in macro declarations and in the bodies of macros, modules and directives. The dummy argument is preceded by a question mark in the places where an actual argument is to be substituted. The question mark distinguishes the dummy arguments from other ABEL-HDL identifiers occurring in the source file.

Take for example, the following macro declaration arguments:

OR_EM MACRO (a,b,c) { ?a # ?b # ?c };

This defines a macro named OR_EM that is the logical OR of three arguments. These arguments are represented in the definition of the macro by the dummy arguments, a, b, and c. In the body of the macro, which is surrounded by braces, the dummy arguments are preceded by question marks to indicate that an actual argument will be substituted.

The equation

D = OR_EM (x,y,z&1);

invokes the OR_EM macro with the actual arguments, x, y, and z&1. This results in the equation:

D = x # y # z&1;

Arguments are substituted into the source file before checking syntax and logic, so if an actual argument contains unsupported syntax or logic, the compiler detects and reports the error.

Argument Guidelines

Dummy arguments are place holders for actual arguments.

A question mark preceding the dummy argument indicates that an actual argument is to be substituted.

Actual arguments replace dummy arguments before the source file is checked for correctness.

Spaces in actual arguments are retained. Usually spaces will not change the functionality, but they are significant with directives that compare two values, such as @ifiden.


Comments

Comments can be entered two ways:

" - Begin the comment with a double quotation mark ( " ) and end with the end of the line or
another double quotation mark.

// - Begin with a double forward slash ( // ) and end with the end of the line (this is useful for commenting out lines of ABEL-HDL source files that contain quote-delineated comments).


Range Operator

The range operator indicates a range of numbers. For example, specifying the set

[A7..A0]

is equivalent to specifying the set

[A7, A6, A5, A4, A3, A2, A1, A0]

The range operator is supported in sets and pin and node declarations.


Sequence of Evaluation

The results of using an operator depend on the sequence of evaluation. Without parentheses, operations are performed from left to right. Consider the following two equations. In the first, the constant 1 is converted to a set; in the second, the 1 is treated as a single bit.

Equation 1: The first operation is [a, b] & 1, so 1 is converted to a set [0, 1].

[x1, y1] = [a, b] & 1 & d
= ([a, b] & 1 ) & d
= ([a, b] & [0, 1]) & d
= ([a & 0, b & 1]) & d
= [ 0 , b ] & d
= [0 & d, b & d]
= [0, b & d]

x1 = 0
y1 = b & d

Equation 2: The first operation is 1 & d, so one is treated as a single bit.

[x2,y2] = 1 & d & [a, b]
= (1 & d) & [a, b]
= d & [a, b]
= [d & a, d & b]

x2 = a & d
y2 = b & d

If you are unsure about the interpretation of an equation, try the following hints:

Fully parenthesize your equation. Errors can occur if you are not familiar with the precedence rules in Operator Priorities.

Write out numbers as sets of 1s and 0s instead of as decimal numbers. If the width is not what you expected, you will get an error message.


Sets

A set is a collection of signals and constants. Any operation applied to a set is applied to each element in the set. Sets simplify ABEL-HDL logic descriptions and test vectors by allowing groups of signals to be referenced with one name.

For example, you could collect the outputs (for example, B0-B7) of an eight-bit multiplexer into a set named MULTOUT, and the three selection lines into a set named SELECT. You could then define the multiplexer in terms of MULTOUT and SELECT rather than individual input and output bits.

A set is represented by a list of constants and signals separated by commas or the range operator (..) and surrounded by brackets. For example,

Sample Set | Description
[B0,B1,B2,B3,B4,B5,B6,B7] | outputs (MULTOUT)
[S0,S1,S2] | select lines (SELECT)

The above sets could also be expressed by using the range operator; for example,

[B0..B7]
[S0..S2]

Identifiers used to delimit a range must have compatible names: they must begin with the same alphabetical prefix and have a numerical suffix. Range identifiers can also delimit a decrementing range or a range which appears as one element of a larger set; for example,

[A7..A0] "decrementing range
[Q1,Q2,.X.,A10..A7] "range within a larger set

For set specifications, the brackets do not denote optional items. The brackets are required to delimit the set. ABEL-HDL source file sets are not mathematical sets.


Set Assignment and Comparison

Values and sets of values can be assigned and compared to a set. are given in the table below. For example,

sigset = [1,1,0] & [0,1,1];

results in sigset being assigned the value, [0,1,0]. The set assignment

[a,b] = c & d;

is the same as the two assignments

a = c & d;
b = c & d;

Numbers in any representation can be assigned or compared to a set. The preceding set equation could have been written as

sigset = 6 & 3;

When numbers are used for set assignment or comparison, the number is converted to its binary representation and the following two rules apply:

If the number of significant bits in the binary representation of a number is greater than the number of elements in a set, the bits are truncated on the left.

If the number of significant bits in the binary representation of a number is less than the number of elements in a set, the number is padded on the left with leading zeroes.

Thus, the following two assignments are equivalent:

[a,b] = ^B101011; "bits truncated to the left
[a,b] = ^B11;

And so are these two:

[d,c] = ^B01;
[d,c] = ^B1; "compiler will add leading zero


Sequence of Evaluation

Operators can act differently when used with sets depending on the types of its arguments. When a set is written

[a, b, c, d]

"a" is the MOST significant bit and "d" is the LEAST significant bit.

The result, when most operators are applied to a set, will be another set. The result of the relational operators (==, !=, >>, >>=, <<, <<=) is a value: TRUE (all ones) or FALSE (all zeros), which is truncated or padded to as many bits as needed. The width of the result is determined by the context of the relational operator, not by the width of the arguments. See examples below.

The different contexts of the AND (&) operator and the semantics of each usage are described below.

& Expression

Example

Result

signal & signal

a & b

The expression is TRUE if both signals are TRUE.

signal & number

a & 4

The number is converted to binary and the least significant bit is used. The expression becomes a & 0, then is reduced to 0 (FALSE).

signal & set

a & [x, y, z]

The signal is distributed over the elements of the set to become [a & x, a & y, a & z]

set & set

[a, b] & [x, y]

The sets are ANDed bit-wise resulting in: [a & x, b & y]. An error is displayed if the set widths do not match.

set & number

[a, b, c] & 5

The number is converted to binary and truncated or padded with zeros as needed to match the width of the set. The sequence of transformations is:

[a, b, c] & [1, 0, 1]
[a & 1, b & 0, c & 1]
[a, 0, c]

number & number

9 & 5

The number is converted to binary and the least significant bit is used, so this expression becomes 1 & 1, which is reduced to 1 (TRUE).

Some example equations:

select = [a15..a0] == ^H80FF

select (signal) is TRUE when the 16-bit address bus has the hex value 80FF. Relational operators always result in a single bit.

[sel1, sel0] = [a3..a0] >> 2

The width of the "sel" set and the "a" set are different, so the "2" is expanded to four bits (of binary) to match the size of the "a" set. Both sel1 and sel2 are true when the value of the four "a" lines (taken as a binary number) are greater than 2. The result of the comparison is a single-bit result which is distributed to both members of the set on the output side of the equation.

[out3..out0] = [in3..in0] & enab

If enable is TRUE, then the values on "in0" through "in3" are seen on the "out0" through "out3" outputs. If enable is FALSE, then the outputs are all FALSE.


Set Indexing

Set indexing allows you to access elements within a set. The following example uses set indexing to assign four elements of a 16-bit set to a smaller set.

declarations
Set1 = [f15..f0];
Set2 = [q3..q0];
equations
Set2 := Set1[7..4];

The numeric values used for defining a set index refer the the bit positions of the set, with 0 being the least significant (left-most) element in the set.

If you are indexing into a set to access a single element, then you can use the following syntax:

declarations
out1 pin istype 'com';
Set1 = [f15..f0];
equations
out1 = Set1[4] == 1;

In this example, a comparator operator (==) was used to convert the single-element set (Set1[4]) into a bit value (equivalent to f4).


Limitations/ Restrictions on Sets

Limitations on Sets

If you have a set assigned to a single value, the value is padded with 0s and then applied to the set. For example,

[A1,A2,A3] = 1

is equivalent to

A1 = 0
A2 = 0
A3 = 1

which may not be the intended result. If you want 1 assigned to each member of the set, you'd need binary 111 or decimal 7. Since the widths of expression arguments are determined from context, there are some cases where the results are not as you might expect. For example, define count as a 3-bit set:

count = [a,b,c]

Then the following expression has a width of one since relational operators evaluate to a single-bit result:

9 & (count == 0)

It is expanded as follows:

9 & ( !a & !b & !c )
1 & !a & !b & !c


Set Operations

Most operators can be applied to sets, with the operation performed on each element of the set, sometimes individually and sometimes according to the rules of Boolean algebra. "Set Operations," found later in this chapter, describes how these operators are applied to sets.

Two-set Operations

For operations involving two or more sets, the sets must have the same number of elements. The expression, "[a,b]+[c,d,e]," is not supported because the sets have different numbers of elements.

For example, the Boolean equation

Chip_Sel = A15 & !A14 & A13;

represents an address decoder where A15, A14 and A13 are the three high-order bits of a 16-bit address. The decoder can easily be implemented with set operations. First, a constant set that holds the address lines is defined so that the set can be referenced by name. This definition is done in the constant declaration section of a module.

The declaration is

Addr = [A15,A14,A13];

which declares the constant set Addr. The equation

Chip_Sel = Addr == [1,0,1];

is functionally equivalent to

Chip_Sel = A15 & !A14 & A13;

If Addr is equal to [1,0,1], meaning that A15 = 1, A14 = 0 and A13 = 1, then Chip_Sel is set to true. The set equation could also have been written as

Chip_Sel = Addr == 5;

because 101 binary equals 5 decimal.

In the example above, a special set with the high-order bits of the 16-bit address was declared and used in the set operation. The full address could have been used and the same function arrived at in other ways, as shown below.

Example 1

" declare some constants in declaration section
Addr = [a15..a0];
X = .X.; "simplify notation for don't care constant
Chip_Sel = Addr == [1,0,1,X,X,X,X,X,X,X,X,X,X,X,X];

Example 2

" declare some constants in declaration section
Addr = [a15..a0];
X =.X.;
Chip_Sel = (Addr >>= ^HA000) & (Addr <<= ^HBFFF);

Both solutions presented in these final two examples are functionally equivalent to the original Boolean equation and to the first solution in which only the high order bits are specified as elements of the set (Addr = [a15, a14, a13]).


Supported Set Operations

Operator | Example | Description
= | A = 5 | combinatorial assignment
:= | A := [1,0] | registered assignment
?= | A ?= [1,0] | combinatorial don't care assignment
?:= | A ?:= 5 | registered don't care assignment
! | !A | NOT: ones complement
& | A & B | AND
# | A # B | OR
$ | A $ B | XOR: exclusive OR
!$ | A !$ B | XNOR: exclusive NOR
- | -A | negate
- | A - B | subtraction
+ | A + B | addition
== | A == B | equal
!= | A != B | not equal
< | A < B | less than
<= | A <= B | less than or equal
> | A > B | greater than
>= | A >= B | greater than or equal


Arithmetic Operators

Operator | Example | Result | Description
- | -A | Twos complement (negation) | dash (minus sign)
- | A-B | Subtraction | dash
+ | A+B | Addition | plus sign

Not Valid for Sets

Operator | Example | Result | Description
* | A*B | Multiplication | asterisk
/ | A/B | Unsigned integer division | forward slash
% | A%B | Modulus: remainder from / | percent sign
<< | A<<B | Shift A left by B bits | double left angle bracket
>> | A>>B | Shift A right by B bits | double right angle bracket

Note A minus sign has a different significance depending on how you use it. When used with one operand, it indicates that the twos complement of the operand is to be formed. When the minus sign is found between two operands, the twos complements of the second operand is added to the first.

Arithmetic operators define arithmetic relationships between items in an expression. The shift operators are included in this class because each left shift of one bit is equivalent to multiplication by 2 and a right shift of one bit is the same as division by 2.

Division is unsigned integer division: the result of division is a positive integer. The remainder of a division can be obtained by using the modulus operator, "%." The shift operators perform logical unsigned shifts. Zeros are shifted in from the left during right shifts and in from the right during left shifts.


Assignment Operators

Operator | Description
= | Combinational or detailed assignment for on-set
:= | Implied registered pin-to-pin assignment for on-set
?= | Combinational or detailed assignment for dc-set
?:= | Implied registered pin-to-pin assignment for dc-set

Caution: The := and ?:= operators are used only when writing pin-to-pin registered equations. If you want to use detailed dot extensions, use the = and ?= operators.

Assignment operators are a special class of operators used in equations rather than in expressions. Equations assign the value of an expression to output signals. See "Equations" below for a complete discussion of equations. There are two assignment operators, combinational and registered. Combinational or immediate assignment occurs without any delay as soon as the equation is evaluated. Registered assignment occurs at the next clock pulse from the clock associated with the output. Refer to the chapter "Design Considerations."

Don't-care Assignment Operators (?= and ?:=)

These assignment operators allow you to fully specify outputs in equations. For example, in the following truth table, the output F is fully specified:

TRUTH_TABLE ([A,B]->[F]);
[1,1]-> 0 ; "off-set
[1,0]-> 1 ; "on-set
[0,1]-> 1 ; "on-set

The equivalent functionality can be expressed in equations:

@DCSET
F = A & !B # !A & B; "on-set
F ?= !A & !B; "dc-set

Note Specifying both the on-set and the don't-care set conditions enhances optimization.

Caution: With equations, @DCSET or ISTYPE 'dc' must be specified or the ?= equations are ignored.


Async_reset and Sync_reset

Syntax

SYNC_RESET symbolic_state_id : input_expression ;
ASYNC_RESET symbolic_state_id : input_expression ;

symbolic_state_id - an identifier used for reference to a symbolic state

input_expression - any valid expression

Use

In symbolic state descriptions, the SYNC_RESET and ASYNC_RESET statements specify synchronous or asynchronous state machine reset logic in terms of symbolic states.

Examples

ASYNC_RESET Start : Reset ;

SYNC_RESET Start : Reset ;


@Alternate - Alternate Operator Set

Syntax

@ALTERNATE

Use

@ALTERNATE brings an alternate set of operators into effect that replace the normal ABEL-HDL operators if you feel more comfortable with the alternate set because of their familiarity with operators used in other languages.

The alternate operators remain in effect until the @STANDARD directive is issued or the end of the module is reached.

Note The use of the alternate operator set precludes use of the ABEL-HDL addition, multiplication and division operators because they represent the OR, AND and NOT logical operators in the alternate set. The !, &, #, $ and !$ will still work when @alternate is in effect.

The table below summarizes the alternate operator set.

Standard Operator | Alternate Operator | Description
! | / | NOT
& | * | AND
# | + | OR
$ | :+: | XOR
!$ | :*: | XNOR


@Carry - Maximum Bit-width for Arithmetic Functions

Syntax

@Carry expression ;

expression - A numeric expression

Use

The @CARRY directive allows you to specify how adders, counters and comparators are generated to reduce the amount of logic required for processing large arithmetic functions. The number generated by the expression indicates the maximum bit-width to use when performing arithmetic functions.

For example, for an 8-bit adder, a @CARRY statement with an expression which results in 2 would divide the 8-bit adder into four 2-bit adders, creating intermediate nodes. This would reduce the amount of logic generated.

The statement:

@CARRY 1;

generates chains of one-bit adders and comparators for all subsequent adder and comparator equations, instead of the full look-ahead carry equations normally generated.

This directive automatically generates additional combinational nodes. Typically, carry chain lengths of 3 or 4 (@carry 3 or @carry 4) is a good trade off between speed and density for Xilinx devices. To specify that full lookahead carry should be generated (the default if no @CARRY has been specified) use the statement:

@CARRY 0;

Example

@carry 2; "generate adder chain
[s8..s0] = [.x.,a7..a0]+[.x.,b7..b0]


@Const - Constant Declarations

Syntax

@CONST id = expression ;

id - A valid identifier

expression - A valid expression

Use

@CONST allows new constant declarations to be made in a source file outside the normal (and required) declarations section.

The @CONST directive is intended to be used inside macros to define internal constants. Constants defined with @CONST override previous constant declarations. Declaring an identifier as a constant in this manner constitutes an error if the identifier was used earlier in the source file as something other than a constant (that is, a macro, pin, device).

Examples

@CONST count = count + 1;


@Dcset - Don't Care Set

Syntax

@DCSET

Use

ABEL-HDL uses don't-care conditions to help in the optimization of partially-specified logic functions. Partially specified logic functions are those that have less than 2n significant input conditions, where n is the number of input signals. The @dcset option allows the optimization to use 1 or 0 for don't cares to optimize these functions.

Caution: The @dcset directive overrides Istype 'dc', 'neg' and 'pos' attributes.


@DCState

Syntax

@dcstate

Use

When @dcstate is specified, all unspecified state diagram states and transitions are applied to the design outputs as don't-cares. This option must be used in combination with @dcset or with the 'dc' attribute.


@Exit - Exit Directive

Syntax

@EXIT

Use

The @exit directive causes the compiler to halt processing of the source file with error bits set. (Error bits allow the operating system to determine that a processing error has occurred.)


@Expr - Expression Directive

Syntax

@EXPR { block } expression;

block - A valid block of text

expression - A valid expression

Use

@Expr evaluates the given expression, and converts it to a string of digits in the default base numbering system. This string and the block are then inserted into the source file at the point at which the @Expr directive occurs. The expression must produce a valid number.

Example

@expr {Addr} 10+4 ;

Assuming that the default base is base ten, this example causes the text ABC3 to be inserted into the source file.


@If - If Directive

Syntax

@IF expression {block}

expression - A valid expression

block - A valid block of text

Use

@IF is used to include sections of ABEL source code based on the value resulting from an expression. If the expression is non-zero (logical true), the block of code is included as part of the source. Dummy argument substitution is valid in the expression.

Example

@IF (A>17) {C = D$F;}


@Ifb - If Blank Directive

Syntax

@IFB (arg) {block}

arg - An actual argument or dummy argument preceded by a "?"

block - A valid block of text

Use

@IFB includes the text contained within the block if the argument is blank (has 0 characters).

Examples

@IFB ()
{ text here will be included with the rest of the source file. }

@IFB ( hello )
{ this text will not be included }

@IFB (?A)
{ this text will be included if no value is substituted for A. }


@Ifdef - If Defined Directive

Syntax

@IFDEF id {block}

id - An identifier

block - A valid block of text

Use

@IFDEF includes the text contained within the block if the identifier is defined.

Example

A pin 5 ;

@IFDEF A {BASE = ^hE000;}
"the above assignment is made because A was defined


@Ifiden - If Identical Directive

Syntax

@IFIDEN (arg1,arg2) {block}

arg1,2 - Actual arguments or dummy arguments preceded by "?"

block - A valid block of text

Use

The text in the block is included in the source file if arg1 and arg2 are identical.

Example

@ifiden (?A,abcd) { ?A device 'P16R4'; }

A device declaration for a P16R4 is made if the actual argument substituted for A is identical to abcd.


@Ifnb - If Not Blank Directive

Syntax

@IFNB (arg) {block}

arg - An actual argument, or dummy arguments preceded by "?"

block - A valid block of text

Use

@IFNB includes the text contained within the block if the argument is not blank, meaning that it has more than 0 characters.

Examples

@IFNB ()
{ ABEL source here will not be included with the rest of the source file. }

@IFNB ( hello )
{ this text will be included }

@IFNB (?A)
{ this text will be included if a value is substituted for A}


@Ifndef - If Not Defined Directive

Syntax

@IFNDEF id {block}

id - An identifier

block - A valid block of text

Use

@IFNDEF includes the text contained within the block if the identifier is undefined. Thus, if no declaration (pin, node, device, macro or constant) has been made for the identifier, the text in the block will be inserted into the source file.

Example

@IFNDEF A {BASE = ^hE000;"
"if A is not defined, the block is inserted in the text


@Ifniden - If Not Identical Directive

Syntax

@IFNIDEN (arg1,arg2) {block}

arg1,2 - Actual arguments, or dummy arguments preceded by "?"

block - A valid block of text

Use

The text in the block is included in the source file if arg1 and arg2 are not identical.

Example

@ifniden (?A,abcd) { ?A device 'P16R8'; }

A device declaration for a P16R8 is made if the actual argument substituted for A is not identical to abcd.


@Include - Include Directive

Syntax

@INCLUDE filespec

filespec - A string specifying the name of a file, where the specification follows the rules of the operating system being used

Use

@INCLUDE causes the contents of the file identified by the file specification to be placed in the ABEL source file. The inclusion will begin at the location of the @INCLUDE directive. The file specification can include an explicit drive or path specification that indicates where the file is to be found. If no drive or path specification is given, the file is expected to be on either the default drive or path.

Examples

@INCLUDE 'macros.abl' "file specification

@INCLUDE '\\incs\\macros.inc' "DOS paths require 2 slashes


@Irp - Indefinite Repeat Directive

Syntax

@IRP dummy_arg ( arg [,arg]... ) {block}

dummy_arg - A dummy argument

arg - An actual argument, or dummy argument preceded by a "?"

block - A block of text

Use

@IRP causes the block to be repeated in the source file n times, where n equals the number of arguments contained in the parentheses. Each time the block is repeated, the dummy argument takes on the value of the next successive argument.

Example

@IRP A (1, ^h0A,0) {B = ?A;}

results in:

B = 1 ;
B = ^H0A ;
B = 0 ;

which is inserted into the source file at the location of the @IRP directive. Multiple assignments to the same identifier cause an implicit OR to occur.


@Irpc - Indefinite Repeat, Character Directive

Syntax

@IRPC dummy_arg (arg) {block}

dummy_arg - A dummy argument

arg - An actual argument, or a dummy argument name preceded by a "?"

block - A valid block of text

Use

@IRPC causes the block to be repeated in the source file n times, where n equals the number of characters contained in arg. Each time the block is repeated, the dummy argument takes on the value of the next successive character.

Example

@IRPC A (Cat)
{B = ?A ;
}

results in:

C ;
B = a ;
B = t ;

which is inserted into the source file at the location of the @IRPC directive.


@Message - Message Directive

Syntax

@MESSAGE 'string'

string - Any valid string

Use

@Message prints a message specified in string to your monitor. This can be used to monitor the progress of compiling, or to debug complex sequences of directives.

Example

@message 'Includes completed'


@Onset

@Onset - Disable @DCSET

Syntax

@ONSET

Use

@ONSET disables the effects of @DCSET for subsequent truth tables and state diagrams. You may enable don't-care optimization with another @DCSET directive.


@Page - Page Directive

Syntax

@PAGE

Use

Send a form feed to the compiler listing file. If no listing is being created, @page has no effect.


@Radix - Default Base Numbering Directive

Syntax

@RADIX expr ;

expr - A valid expression that produces the number 2, 8, 10 or 16 to indicate a new default base numbering

Use

@Radix is used to change the default base numbering system. The default is base 10 (decimal). This directive is useful when many numbers need to be specified in a base other than 10. The @radix directive can be issued and all numbers that do not have their base explicitly stated are assumed to be in the new base. (See the chapter "Language Elements.")

Examples

@radix 2 ; "change default base to binary

@radix 10 ; "change to decimal


@Repeat - Repeat Directive

Syntax

@REPEAT expr {block}

expr - A valid expression that produces a number

block - A valid block of text

Use

@REPEAT causes the block to be repeated n times, where n is specified by the constant expression.

Example

The following use of the repeat directive,

@repeat 5 {H,}

results in the text "H,H,H,H,H," being inserted into the source file.


@Setsize - Set Indexing

Syntax

@SETSIZE

Use

The @Setsize directive generates a number corresponding to the number of elements in the expression, which must be a set. This directive is useful for set indexing operations.

Example

@setsize [a,b,c]

generates the number 3.

For set indexing, the @Setsize directive can be used in macros as follows:

high macro (s) {?s[@setsize(?s); -1..@setsize(?s);/2-1};

The high macro returns the upper half of a set of any size (the high 4 bits of an 8-bit set, for example).

Note The terminating semicolons are required.


@Standard - Standard Operators Directive

Syntax

@STANDARD

Use

@Standard switches the operators in effect back to the ABEL standard operators from the alternate set. The alternate set is chosen with the @Alternate directive.


4-Bit Comparator

The following design illustrates the implementation of a 4-bit comparator that provides outputs for ''equal to'', ''less than'', ''not equal to'', and ''greater than'' (as well as intermediate outputs). The design is implemented with high-level equations.

Design Specification

The comparator compares the value of two 4-bit inputs (A0-A3 and B0-B3) and determines whether A is equal to, not equal to, less than, or greater than B. The result of the comparison is shown on the output lines EQ, NE, LT, and GT.

Design Method

The following figure shows the simplified block diagram for the comparator. The inputs are grouped into the sets A and B.

The equations section of the source file contains the following equations:

EQ = A == B;
NE = !(A == B);
GT = A > B;
LT = !((A > B) # (A == B));

You could also use the following equations, however many more product terms would be required:

EQ = A == B;
NE = A != B;
GT = A > B;
LT = A < B;

The first set of equations takes advantage of product term sharing within the target device, while the second set requires a different set of equations for each equation. For example, the equation:

NE = !(A == B);

uses the same 16 product terms as the equation:

EQ = A == B;

thereby reducing the number of product terms. In a similar manner, the equation:

LT = !((A > B) # (A == B));

uses the same product terms as equations:

EQ = A == B;
GT = A > B;

Whereas (in the second set of equations) the equation:

LT = A < B;

requires the use of additional product terms. Sharing product terms helps to fit designs into smaller devices.

4-Bit Comparator Source File

module comp4a

title '4-bit lookahead comparator

Xilinx'

comp4a device 'F153';

A3..A0 pin 1..4;

A = [A3..A0];

B3..B0 pin 5..8;

B = [B3..B0];

NE,EQ,GT,LT pin 16..19 istype 'com';

No,Yes = 0,1;

equations

EQ = A == B;

NE = !(A == B);

GT = A > B;

LT = !((A > B) # (A == B));

''test_vectors deleted...

end


4-Bit Universal Counter

The following design illustrates the implementation of a 4-bit up/down counter with parallel load and count enable. The design is described using high-level ABEL-HDL equations. The following figure shows the block diagram of the counter.

The outputs q3, q2, q1, and q0 contain the current count. The least significant bit (LSB) is q0.

Using Sets to Create Modes

The counter has four modes of operation:

  • Load data from the inputs.

  • Count up.

  • Count down.

  • Hold count.

You select the modes by applying various combinations of values to the inputs cnten, ld, and u_d, as described below. The four modes have different priorities, which are defined in the ABEL-HDL description.

  • Load Mode - Has the highest priority. If the ld input is high, then the q outputs reflect the value on the d inputs after the next clock edge.

  • Hold Mode - Has the second highest priority. If ld is low, then when the cnten input is low, the q outputs maintain their current values upon subsequent clock edges, ignoring any other inputs.

  • Up and Down Modes - These have the same (least) priority and by definition are mutually exclusive (only one can be enabled at a time). If cnten is high and ld is low, then when u_d is high the counter counts up and when u_d is low the counter counts down.

Counter Reset

The counter is reset asynchronously by the rst input.

Using Range Operators

Because this design uses range operators and sets, you can modify the counter to be any width by making changes in the declaration section. You could create a 9-bit counter by changing the lines which read ''d3..d0'' and ''q3..q0'' to ''d8..d0'' and ''q8..q0,'' respectively. The range expressions are expanded out and create register sets of corresponding width.

Hierarchical Interface Declaration

Directly after the module name, the design contains a hierarchical interface declaration which is used by the ABEL-HDL compiler and linker if another ABEL-HDL source instantiates this source. The interface list shows all of the input, output, and bidirectional signals (if any) in the design.

Declarations

The declarations contain sections that make the design easier to interpret. The sections are:

Constants | Constant values are defined
Inputs | Design inputs are declared
Outputs | The output pin list contains an istype declaration for retargetability
Sets | The names data and count are defined as sets (groups) containing the inputs d3,d2, d1, and d0, and the outputs q3, q2, q1, and q0, respectively.
Modes | The ''Mode equations'' are actually more constant declarations. First MODE is defined as the set containing cnten, ld, and u_d in that order. Next, LOAD is defined as being true when the members of MODE are equal to X, 1, and X, respectively. HOLD, UP, and DOWN are defined similarly.

Equations

The design of the counter equations enables you to easily define modes and your actual register equations will be easily readable. The counter equation uses when-then-else syntax. The first line:

when LOAD then count := data

uses the symbolic name LOAD, defined earlier in the source file as:

LOAD = (MODE == [X, 1, X])

and MODE itself is a set of inputs in a particular order, defined previously as:

MODE = [cnten, ld, u_d]

The first line of the equation could have been written as follows:

when ((cnten == X) & (ld == 1) & (U-D == X)) then count := data;

which is functionally the same, but the intermediate definitions used instead makes the source file more readable and easier to modify.

4-Bit Universal Counter Source File

module unicnt

interface (d3..d0, clk,rst,ld, u_d -> q3..q0);

title '4-bit universal counter with parallel load

Xilinx';

''Constants

X,C,Z = .X., .C., .Z.;

''Inputs

d3..d0 pin; ''Data inputs, 4-bits wide

clk pin; ''Clock input

rst pin; ''Asynchronous reset

cnten pin; ''Count enable

ld pin; ''Load counter with input data value

u_d pin; ''Up/Down select - High=up

''Outputs

q3..q0 pin istype 'reg'; ''Counter outputs

''Sets

data = [d3..d0]; ''Data set

count = [q3..q0]; ''Counter set

''Mode equations

MODE = [cnten,ld,u_d] ; ''Mode set made of control pins

LOAD = (MODE == [ X , 1, X ]); ''Various modes are defined by

HOLD = (MODE == [ 0 , 0, X ]); ''values applied to control pins.

UP = (MODE == [ 1 , 0, 1 ]); ''Symbolic name may be defined as

DOWN = (MODE == [ 1 , 0, 0 ]); ''a set equated to a value.

Equations

when LOAD then count := data ''Load counter with data

else when UP then count := count + 1 ''Count up

else when DOWN then count := count - 1 ''Count down

else when HOLD then count := count; ''Hold count

count.clk = clk; ''Counter clock input

count.ar = rst; ''Counter reset input

Test_vectors edited...

End


Blacjack Machine Description

Blackjack Machine Description

This design is the combination of more than one basic logic design. Design specification, methods, and complete source files are provided here for all parts of the blackjack machine example, which contains the following logic designs:

  • Multiplexer

  • -bit adder

  • Binary to BCD converter

  • State machine

This example is a classic blackjack machine based on C.R. Clare's design in Designing Logic systems Using State Machines (McGraw Hill, 1972). The blackjack machine plays the dealer's hand, using typical dealer strategies to decide, after each round of play, whether to draw another card or to stand.

The blackjack machine consists of these functions:

  • Card Reader - Reads each card as it is drawn. (Neither the card reader nor the physical design is discussed here. Assume that the card reader provides a binary value representing the card read.)

  • Control Logic - Tells it how to play each hand (based on the total point value of the cards presently held).

  • Display Logic - Displays scores and states on the machine's four LED displays.

Note For this design, the two 7-segment displays have built-in 7-segment decoders.


Blackjack Machine - BINBCD

Outputs that do not follow a specific pattern are most easily expressed as truth tables. This is the case with the BCD converter, BINBCD. This PLD converts five bits of binary input to BCD output for the 7-segment displays.

Design Method

Design Specification

Source File

Test Vectors


Blackjack Machine - BJACK

BJACK is a state machine, demonstrating how to create and implement state diagrams.

Design Specification

Design Method

State_Machine_Operation_BJACK

State Diagram

Test Vectors

Source File


Blackjack Machine Implementation

The blackjack machine is implemented in three PLDs:

  • A multiplexer-adder-comparator, (MUXADD) which adds the value of the newly drawn card to the existing hand and indicates an ace to the state machine.

  • A binary-coded-decimal (BCD) converter, (BINBCD) which takes in the 5-bit binary score and converts it to two digits of BCD for the digital display.

  • The blackjack controller, (BJACK) which is a state machine that contains the game logic. This logic includes instructions that determine when to add a card value, when to count an ace as 1, and when to count an ace as 11.


Blackjack Machine - MUXADD PLD

Circuits that are a straight forward function of a set of inputs and outputs are often most easily expressed in equations; the adder within the MUXADD PLD is such a circuit. The PLD includes three elements: a multiplexer, the adder, and a comparator.

The multiplexer selects either the value of the newly dealt card or one of the two fixed values used for the ace (ADD10 or SUB10). The adder adds the value selected by the multiplexer to the previous score when triggered by the click signal ADDCLK. The comparator detects when an ace is present and passes this information on to the blackjack controller, BJACK.

Design Specification

Design Method

Test Vectors

Source File


Blackjack Machine Operation

To operate the machine, insert the dealer's card into the card reader. The machine reads the value and, in the case of later card draws, adds it to the values of the previously read cards for that hand. Face cards are worth 10 points, non-face cards are worth their face value, and aces are worth either 1 or 11 (whichever yields the best hand). If the point total is 16 or less, the GT16 line is asserted and the HIT LED lights up; this indicates the dealer should draw another card. If the point total is greater than 16 but less than 22, no LEDs light up, indicating that the dealer should not draw any more cards. If the point total is 22 or higher, the LT22 line is asserted and the BUST LED lights, indicating that the dealer lost the hand.


BUS Keyword

Syntax

BUS [3..0]q

PIN istype 'reg';

This example declares a BUS pin named 'q' which is 4 bits wide, with a MSB of 3 and a LSB of 0. Usage rules and supported operators for BUSes in Abel are basically the same as for SETs. When referencing a bus in ABEL code you must always include the '[' and ']' characters to specify which bits of the bus you are referring to. For example:

q[0] // selects the least significant bit of q.

q[3..2] // selects the two most significant bits of q.

q[3..0] // selects all bits of q.

Use

The BUS keyword can prefix the declaration of a PIN or NODE

The following is an example of using a BUS in an equation:

WHEN (dir==1) then { q[3..1] := q[2..0];

q[0] := !q[3]; }

else { q[2..0] := q[3..1];

q[3] := !q[0]; }


Case Keyword

Syntax

CASE [ expression : state_exp; ]
[ expression : state_exp; ]
[ expression : state_exp; ]
:
ENDCASE ;

Use

The CASE statement is used under the State_diagram section to indicate the transitions of a state machine when there are multiple possible conditions that affect the state transitions.

You can nest Case statements with If-Then-Else, Goto, and other Case statements, and you can use equation blocks.

Example

case a == 0 : 1 ;
a == 1 : 2 ;
a == 2 : 3 ;
a == 3 : 0 ;
endcase ;


Clock Divider Implemenation (ABEL)

The clock divider feature is for CoolRunner-II devices only, XC2C128 and above. The clock divider can be implemented by instantiating a CLK_DIVx[R][SD] in Abel using the EXTERNAL and FUNCTIONAL_BLOCK constructs.

Example:

clk_in PIN;

clk_divided NODE;

q PIN istype 'REG';

// external declarations for CRII clock divider macros.

CLK_DIV2 EXTERNAL (CLKIN -> CLKDV);

// instance of CRII clock divider macro.

my_clkdiv2 FUNCTIONAL_BLOCK CLK_DIV2;

EQUATIONS

// instantiate clock divider.

my_clkdiv2.CLKIN = clk_in;

clk_divided = my_clkdiv2.CLKDV;

q.CLK = clk_divided;

...

Note Simulation of the clock divider and dual-edge flops in blifsim is not supported.


Combined Logic Descriptions

Blackjack Machine

This topic contains an advanced logic design (a blackjack game machine) and builds on examples and concepts presented in the previous sections.

Description

Operation

Implementation

The following schematic shows the implementation of this design:


Device-independent ABEL-HDL Sources

Most of the ABEL-HDL language is device-independent (for example, equations, truth tables, state machine descriptions and test vectors). However, the ABEL-HDL compiler needs some information describing how signals should function in logic descriptions. Some devices also have special functions that are accessed through conditionally-compiled syntax.

Information needed | Provided in ABEL-HDL with
Output signal specifications | Istype attributes in the signal declarations and dot extensions on signals in the logic description.
Special functions | Property Statements

Most common signal functions can still be described independent of a device with the pin-to-pin signal declarations. Some special features available in only certain classes of devices require device-specific signal declarations.

Pin-to-Pin Signal Specifications

Using ABEL-HDL's pin-to-pin syntax allows you to create logic descriptions that can be retargeted to different devices. We recommend you use the pin-to-pin syntax whenever you have a choice to allow the source to be retargeted with little modification.

Detailed Signal Specifications

Device-specific signal specification allows you to take advantage of unique features found only in certain device families.

Note You can combine pin-to-pin and detailed signal declarations. In most cases, the ABEL-HDL compiler can reconcile the requirements of both types. In cases where the circuit function is ambiguous, the compiler displays an error message.

The ABEL-HDL syntax descriptions indicate whether the syntax is pin-to-pin or detailed.


Constants

Constant, non-changing values can be used in ABEL-HDL logic descriptions. Constant values are used in assignment statements, truth tables and test vectors, and are sometimes assigned to an identifier that then denotes that value throughout a source file. Constant values can be numeric, or one of the non-numeric special constant values.


Declarations Keyword

Syntax

DECLARATIONS
declarations

Use

A declaration is any valid declaration given after the Declarations keyword. Declarations can be declared in any part of the ABEL-HDL source file.

Example

module andor

A,B pin 1,2; "declarations keyword implied
Out1 pin 15 istype 'com';

Equations
Out1 = A & B;

Declarations "declarations keyword required
C,D,E,F pin 3,4,5,6;
Out2 pin 16 istype 'com';
Temp1 = C & D;
Temp2 = E & F;

Equations
Out2 = Temp1 # Temp2;

end;


Design Method - BINBCD

The design of the BCD converter is easily expressed with a truth table that lists the value of Score (S0-S4), for values of bcd1 and bcd2, up to scores of decimal 31.

The truth table in this design expresses the design manually. However you could also use a macro to create a truth table as follows:

clear (binary);
@repeat 32 { binary - [binary/10,binary%10];
inc(binary);}

This macro is used to generate the test vectors.

A pair of equations generate an active-high LT22 signal to turn off the BUST LED when Score is less than 22, and an active-high GT16 signal to turn off the HIT LED when Score is less than 16.


Design Method - BJACK

Developing a bubble diagram is the first step in describing a state machine. The BJACK state diagram indicates the state transitions and the conditions that cause those transitions. There is a one-to-one correlation between the bubble diagram and the state diagram described in the source file. The following table describes the state identifiers (state machine states) illustrated in the bubble diagram and listed in the source file:

State Identifier | Description
Clear | Clear the state machine, adder, and displays.
ShowHit | Indicate that another card is needed. Light the HIT indicator.
AddCard | Add the adder input to the current count.
Add10 | Add 10 to the current count, giving an ace a value of 11.
Wait | Wait until a card is taken from the reader.
Test17 | Test the current count for a value less than 17.
Test22 | Test the current count for a value less than 22.
Sub10 | Add -10 to the count, restoring an ace to 1.
ShowBust | Indicate no more cards are needed. Light the BUST indicator.
ShowStand | Indicate no more cards are needed. Hit and BUST are not lit.


Design Method - MUXADD

MUXADD is implemented in a P22V10, and consists of a 3-input multiplexer, a 5-bit ripple adder, and a 5-bit comparator. For the multiplexer inputs, a set named Card defines inputs V0-V4 as the value of the card reader, while inputs ADD10 and SUB10 are used directly in the following equations to define the multiplexer. The multiplexer output to the adder is named Data and is defined by the equations:

DATA = ADD10 & SUB10 & Card
# !ADD10 & SUB10 & ten
# ADD10 & !SUB10 & minus_ten;

The adder is a 5-bit binary ripple adder that adds the current input from the multiplexer to the current score, with carry. The adder is clocked by AddClk from the BJACK controller and is described with the equations:

Score := Data $ Score.fb $ CarryIn;
CarryOut = Data & Score.fb # (Data # Score.fb) & CarryIn;
Reset = !Clr;

In these equations, Score is the sum of Data, Score (the last calculated score), and CarryIn (the shifted value of CarryOut). The new value of Score appears at the S0-S4 outputs of MUXADD at the time of the AddClk pulse from BJACK.

Before the AddClk pulse, an intermediate adder output, labeled C0-C4, appears and is defined as the set named CarryOut. A second set named CarryIn defines the same combinational outputs as CarryOut, but the outputs are shifted one bit to the left, as follows:

CarryIn = [C4..C1, 0];
CarryOut = [X ,C4..C1];

The set declarations define CarryIn and CarryOut with the required shift to the left for application back to the adder input. At the time of the AddClk pulse, CarryIn is added to Score and Data by an exclusive-OR operation.

The comparator of MUXADD is defined with:

is_Ace = Card == 1;

which provides an input to BJACK whenever the value of the card is 1.


Design Specification - BINBCD

To display the Score, a binary to BCD converter is implemented. This converter accepts the four bits of binary data from MUXADD and provides two sets of BCD outputs for the two 7-segment displays. One displays the units of the current score, the other displays the tens; bcd1 (D0-D3) drives the units, and bcd2 (D4-D5) drives the tens.

BINBCD also outputs BUST when Score is 22 or greater, and HIT when Score is 16 or less.


Design Specification - BJACK

BJACK is a state machine which stores the states that reflect the following conditions:

  • The value of Score in on of the ranges of 0-16, 17-21, or 22+.

  • The status of the card reader (card in or card out).

  • The presence of an ace in the card reader.

On the basis of these stored states, and input from each new card, the controller decides whether or not a +10 or a -10 value is sent to the adder.


Design Specification - MUXADD

MUXADD consists of an input multiplexer, an adder, and a comparator. The multiplexer determines what value is added to the current score. The added value consists of the contents of the external card reader (V0-V3 declared as Card), a numeric value of +10, or a numeric value of -10.

The inputs ADD10 and SUB10 from the controller BJACK determines which value the multiplexer selects for the adder. Card is applied to the adder when ADD10 and SUB10 are high. When ADD10 goes low, 10 is added to the current score (to count an ace as 11 instead of 1). When SUB10 is low, -10 is added to the score (To count an ace as 1 instead of 11). The adder output is named score (S0-S4). The comparator monitors the card reader and generates the output is_Ace to BJACK signifying that an ace is present.


Detailed Dot Extensions

Detailed Dot Extensions for CPLD Designs

Dot Extensions Used in the Left Hand Side of Equations

Dot Extensions Used in the Right Hand Side of Equations


Detailed Example

This example describes a 2-bit counter that uses the built-in register reset of some devices.

module count
q0,q1 pin istype 'reg,buffer';
clock pin;
reset pin ;
equations
[q1,q0].clk = clock;
[q1.D,q0.D] = [q1.Q,q0.Q] + 1;
[q1.SR,q0.SR] = reset;
test vectors ([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
:
end

Pin-to-pin design methods cannot be used for this form of the design, since there is no pin-to-pin syntax for describing reset logic for built-in reset features. This design uses an istype 'buffer' declaration to ensure that the flip-flop reset propagates to the pin without an unwanted inversion.

Note When you describe a preset or reset function with a detailed description, you need to include an 'invert' or 'buffer' attribute. If you specify 'invert', the preset logic is reversed (and acts as a reset when observed from the pin).


Device Keyword

Syntax

device_id DEVICE real_device ;

device_id - An identifier used for the programmer to load filenames

real_device - A string describing the architecture name of the real device represented by device_id. Only supported devices can be specified.

Use

The device declaration is optional. It associates the device name used in a module with an actual programmable logic device on which designs are implemented. Device identifiers used in device declarations should be valid filenames since JEDEC files are created by appending the extension .jed to the identifier. The ending semicolon is required.

Example

D1 DEVICE 'P16R4' ;


Directives

@directive - Directives

Purpose

Directives affect the contents of a source file when it is processed. Sections of ABEL-HDL source code can be included conditionally, code can be brought into a source file from another file, and messages can be printed during the processing of a source file. The available directives are given on the following pages.

Use

Directives allow you to use more complex structures.

Some of the directives use arguments to determine conditions. The arguments can be actual arguments, or dummy arguments preceded by question marks (?).

@Alternate | @Carry | @Const
@Dcset | @Dcstate | @Exit
@Expr | @If | @Ifb
@Ifdef | @Ifiden | @Ifnb
@Ifndef | @Ifniden | @Include
@Irp | @Irpc | @Message
@Onset | @Page | @Radix
@Repeat | @Setsize | @Standard


END Keyword

Syntax

END [module_name]

Use

The END statement is paired with the MODULE statement. See the help section on MODULE for more information.

Example

end source


Equation Blocks

Equation blocks let you specify more complex functions and improve the readability of your equations. An equation block is enclosed in braces ({}), and is supported wherever a single equation is supported. Within a conditional expression, such as If-Then, Case, or When-Then, equation blocks result in logic functions that are logically ANDed with the conditional expression that is in effect.

Example

state 5 : IF a == 1 then 1
WITH {x : = 1 ;
y : = 1 ;};
ELSE 2 WITH {x : = 0 ;
y : = 1 ;};


= Constant Declarations

Syntax

id [,id]... = expr [,expr]... ;

id - The id is an identifier that names a constant to be used within a module.

expr - The expr is an expression that defines the constant value.

Use

A constant declaration defines constants used in a module.

Note The equal sign (=) used for constant declarations in the Declarations section is also used for equations in the Equations section. See Operators.

The identifiers on the left side of the equals sign are assigned the values listed on the right side. There is a one-to-one correspondence between the identifiers and the listed expressions. There must be one expression for each identifier.

The ending semicolon is required after each declaration.

Constants are useful when a value is repeated many times in a module, especially when the value may be changed during the design process. Rather than changing the value throughout the module, the value can be changed once in the declaration of the constant.

Constant declarations may not be self-referencing; for example:

X = X;

will cause errors, as will the declarations

a = b;
b = a;

An include file, constants.inc, is supplied with ABEL and contains definitions for the most frequently used ABEL-HDL constants. This file may be included in your design with the command:

Library 'constants' ;

Examples:

ABC = 3 * 17; " ABC is assigned the value 51
Y = 'Bc' ; " Y = + H4263 ;
X =.X.; " X means 'don't care'
ADDR = [1,0,15]; " ADDR is a set with 3 elements
A,B,C = 5,[1,0],6; " 3 constants declared here

D pin 6; " see next line
E = [5 * 7,D]; " signal names can be included
G = [1,2]+[3,4]; " set operations are legal
A = B & C; " operations on identifiers are valid
A = [!B,C]; " set and identifiers on right


Equations Keyword

Syntax

EQUATIONS
element [?]:= condition ;
element [?]= condition ;

Use

The equations statement defines the beginning of a group of equations associated with a device. Equations specify logic functions with Boolean algebra. An ending semicolon is required after each equation.

Use When-then-else for conditional expressions in equations. If-then-else is used only in State_diagram descriptions.

Caution: The := and ?:= assignment operators are used only when writing pin-to-pin registered equations. Use the = and ?= assignment operators for registered equations using detailed dot extensions.

Example

equations
A = B & C # A ;
[W,Y] = 3 ;
!F = B == C ;
output.D = in1 # in2 ;


Equation Examples

This section will help you understand how to write ABEL-HDL equations by showing you how the following common functions are created:

Memory Address Decoder

12-to-4 Multiplexer

4-Bit Universal Counter

4-Bit Comparator


Expressions

Expressions are combinations of identifiers and operators that produce one result when evaluated. Any logical, arithmetic or relational operators may be used in expressions.

Expressions are evaluated according to the particular operators involved. Some operators take precedence over others, and their operation is performed first. Each operator has been assigned a priority that determines the order of evaluation.


Feedback Rules

Xilinx fitters use the following feedback rules:

  • If the device specified has a pin feedback path, use the pin feedback.

  • If there is no pin feedback path, and the device has a register feedback path, use the register feedback path and normalize the feedback signal to the pin.

  • Do not consider the state of the output enables (in either case).

Following these rules, the counter design presented earlier would operate incorrectly if implemented in a device with a pin feedback path, since no output enable logic was specified. In devices with multiple feedback paths, the pin feedback takes precedence over the register feedback path when no dot extension is specified.


Feedback Normalization

Feedback normalization is the term used to describe the conversion of feedbacks to a standard polarity. The standard most often used is the polarity observed on the device output pin. Since feedbacks (both registered and combinational) can originate from a wide variety of macrocell locations, it is important to normalize feedbacks so that the same design description can be mapped to a wide variety of devices.

Register feedback is normalized to one of two locations in a device. When a feedback is specified as .FB, or with no dot extension, the signal fed back to the array is normalized to the output pin, regardless of the actual source of the feedback. When register feedback is specified with .Q, the signal fed back to the array is normalized to the Q output of the associated flip-flop ? again regardless of the actual source of the feedback.


Feedbacks Specified Without Dot Extensions

When a registered signal is specified with no feedback dot extension as a reference, the results depend on the type of device that is selected for fitting. If the device selected has multiple feedback paths (for example, registered and combinational, or register and pin) then the feedback is ambiguous, and the results can be difficult to determine.

For example, consider the following simple counter design.

module count
q0,q1 pin istype 'reg';
clock pin;
reset pin;
equations
[q1,q0].clk = clock;
[q1,q0] := ([q1,q0] + 1) & !reset;

test_vectors
([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 0, 0];
end

Since the q0 and q1 signals have not been referenced in the equations with feedback dot extensions, the operation of the circuit can differ depending on the device selected. The Equation Simulator and all Device Kit fitters created by Xilinx follow the same feedback rules when mapping unspecified feedbacks to devices.


Feedback Specification - .Q and .FB

The .Q and .FB dot extensions both specify that the associated flip-flop is the source of the feedback signal, but the polarity of the resulting feedback signal may differ depending on the macrocell configuration. The figure below demonstrates the difference.

The first macrocell has an inverted output pin, but the second macrocell has a non-inverted output pin. The output inversion in the first diagram corresponds to the istype 'invert' attribute in ABEL-HDL. The second diagram corresponds to istype 'buffer'. In the inverted diagram, the .Q feedback dot extension is the complement of the .FB dot extension; while in the non-inverted diagram, the two dot extensions are identical.

In the above figure, the feedback path is shown as though it originated at the Q output of the flip-flop. In actuality, the feedback usually originates at the Q-bar output of the flip-flop, but the result is the same: the feedback paths are adjusted automatically to reflect the actual source of the signal:


Device Fitters and Register Feedback

There are cases where even a fully-specified feedback can be implemented differently in different devices. For example, the global macrocells of the E1800 feature multiple feedback paths.

To map an equation that uses .FB for feedback, the device fitter and the Fuseasm fuse mapper have two paths to choose from. If the feedback needs to be global (distributed outside of the local quadrant of the device) then the pin feedback must be used in place of the register feedback. To accommodate situations like this, Xilinx fitters and the Fuseasm program use the following set of rules when interpreting .FB and .Q feedback specifications:

  • If the device has a direct register feedback path, then use the register feedback path.

  • If the feedback was specified with .FB, then normalize the polarity to the device output pin.

  • If the feedback was specified with .Q, then normalize the polarity to the Q output of the associated flip-flop.

  • If there is no direct register feedback path available, then use the pin feedback path, and ensure that the output enable (if any) is permanently enabled.

  • If conflicting output enable logic was specified in the design, then report an error.

  • If the device has a pin-controlled output enable, then report a warning error to remind the user to tie the enable pin to the appropriate enabling value.

  • If the feedback was specified with .FB, then normalize polarity to the output pin.

  • If the feedback was specified with .Q, then normalize the polarity to the Q output of the associated flip-flop.


Functional_block Keyword

Syntax

DECLARATIONS
instance_name FUNCTIONAL_BLOCK module_name
EQUATIONS
instance_name.port_name = signal_name; :

instance_name - A unique identifer for this instance of the functional block in the current source.

module_name - The name of the lower-level source being instantiated.

port_name - The name of an input or output port from the lower-level source.

signal_name - The signal or signal set by which the ports (inputs and outputs) in the lower-level source are referenced for that instance of the source.

Purpose

You use a functional_block declaration in a top-level ABEL-HDL source to instantiate a declared lower-level source and make the ports of the lower-level source accessible in the top-level source. You must declare sources with an interface declaration before you instantiate them with a functional_block statement.

Note The output of an equation must always be on the left side of the equations.

Note When a source is instanced by a top-level module, any signal attributes (either explicit or implicit) are inherited by the top-level module signals. Therefore, you do not need to specify ISTYPEs in top-level sources for instantiated signals.

Creating Multiple Instances

You can use the range operator (..) to instantiate multiple instance names of the source. For example,

CNT0..CNT3 functional_block cnt4 ;

creates 4 instances of the submodule cnt4.

Mapping Ports to Signals

Signal names are mapped to port names using equations (similar to wiring the signals on a schematic). You need to specify only the signals used in the top-level source if default values have been specified in the lower-level source interface statement. See Interface (lower-level source) for more information on setting default values.

To specify the signal wiring, map signal names to the submodule port names with dot extension notation. There are three kinds of wire: input, output, and interconnect.

Input Wire

Connects submodule outputs to top-level source inputs.

instance.port = input

Output Wire

Connects top-level source outputs to lower-level source inputs.

output = instance.port

Interconnect Wire

Connects the outputs of one instance of a submodule to another instance's inputs.

instance0.port = instance1.port

Example

module counter;
cnt4 interface (ce, ar, clk -> [q0..q3]); "cnt4's top-level interface declaration. CNT0..CNT3 functional_block cnt4; "Four instances of cnt4

Clk, AR, CE pin;
Q0..Q3 pin;

equations
CNT0.[clk,ar,ce]=[Clk,AR,CE]; "Connecting to Clk, AR, and CE inputs.
[Q0..Q3] = CNT0.[q0..q3] ; "Connecting to Q0..Q3 outputs.
end

The above file instantiates four instances of cnt4, but only one (CNT0) is wired.

Overriding Default Values

You can override the default values given in a lower-level source's interface statement by specifying default equations in the top-level source. For example, if you have specified a default value of 1 for the signal ce in interface cnt4 but in instance CNT0, you want ce to be 0, you would write:

CNT0.ce = 0 ;

This equation overrides the 1 with a 0. If you override the default values, you may want to re-optimize the post-linked design.

Unused Outputs (No Connects)

If you do not want to use a submodule's outputs, you can specify them as No Connects (NC) by not wiring up the port to a physical pin. For example, to make a 3-bit counter out of a 4-bit counter in the top-level module, you might use the following wiring equations:

q2..q0 pin ; "top-level signals
Equations
[q2..q0] = CNT_A.[q2..q0]


Fuses Keyword

This keyword is not supported for Xilinx designs.


Goto Keyword

Syntax

GOTO state_exp ;

state_exp - An expression identifying the next state, optionally followed by WITH transition equations.

Use

The GOTO statement causes an unconditional transition to the state indicated by state_exp. GOTO statements can be nested with If-Then-Else, CASE, and With statements.

Examples

GOTO 0 ; "goto state 0

GOTO x+y ; "goto the state x + y


How Equations Use Expressions

Equations assign the value of an expression to a signal or set of signals in a logic description. The identifier and expression must follow the rules already established for those elements.

Equations use the assignment operators = and ?= (combinational), and := and ?:= (registered).

The complement operator, "!," can be used to express negative logic. The complement operator precedes the signal name and implies that the expression on the right of the equation is to be complemented before it is assigned to the signal. Use of the complement operator on the left side of equations is provided as an option; equations for negative logic parts can just as easily be expressed by complementing the expression on the right side of the equation.


If-Then-Else Keyword

Syntax

IF expression THEN state_exp
[ ELSE state_exp ] ;

Chained IF-THEN-ELSE

IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE IF expression THEN state_expression
ELSE state_expression ;

expression - Any valid expression.

state_exp - An expression identifying the next state, optionally followed by WITH transition equations.

Use

The IF-THEN-ELSE statement is an easy way to describe the progression from one state to another in a state machine. The expression following the IF keyword is evaluated, and if the result is true, the machine goes to the state indicated by the state_exp following the THEN keyword. If the result of the expression is false, the machine advances to the state indicated by the ELSE keyword.

Additional IF-THEN-ELSE statements can be chained to the ELSE clause of an IF-THEN-ELSE statement. Any number of IF-THEN-ELSE statements can be chained, but the final statement must end with a semicolon.

Note Equation blocks used within a conditional expression, such as If-Then-Else, result in logic functions that are logically ANDed with the conditional expression that is in effect.

Caution: If-Then-Else is only supported within a state_diagram description. Use When-Then-Else for equations.

Example

If A==B then 2 ; "if A equals B goto state 2
if x-y then j else k; "if x-y is not 0 goto j, else goto k
if A then b*c; "if A is true (non-zero) goto state b*c

Chained If-Then-Else

if a then 1
else
if b then 2
else
if c then 3
else 0 ;


Interface - Declare Modules for Hierarchical Designs

Interface - Declare Lower-level Sources for Hierarchical Designs

The interface keyword is used for hierarchical designs to pass signal names from lower-level sources to the top-level sources that use those signals. To create a hierarchical design, you need the following

In the top-level source:

  • An interface declaration for the lower-level source.

  • One or more functional_block statements instantiating the lower-level source for use in the top-level source.

In the lower-level source:

  • An interface declaration of the signals that can be used by top-level sources, and an optional default value for the input signals.


Interface Keyword (lower-level)

Interface Keyword (lower-level source)

Syntax

MODULE module_name
INTERFACE (input/set[=value] -> output/set [:> bidir/set]);

module_name - The standard module statement for the ABEL-HDL source.

signal/set - Signals or sets in the lower-level module used as ports to top-level modules. Use -> and :> to indicate the direction of each port of a functional block. Use commas to separate groups of signals

value - The default value for the port for input signals only. Default values do not apply to output and bidirectional signals.

Purpose

The interface declaration is optional for lower-level modules. Use the interface declaration in lower-level modules to assign a default port list and input values for the module when instantiated in top-level ABEL-HDL sources. If you use the interface statement in an instantiated module, you must declare the signals and sets in the top-level source in the same order and grouping as given in the interface statement in the lower-level module.

Declaring signals in the lower-level module, although optional, does allow the compiler to check for signal declaration mismatches and therefore reduces the possibility of wiring errors.

Declared Signals

Declared signals can be a list of lower-level pins, sets or a combination of both. The following constraints apply to the different signal types:

Signal Type | Constraints
Input | Default values must be binary if applied to an individual bit, or any positive integer applied to a set. All inputs must be listed.
Output | Unlisted outputs are interpreted as No connects (NC). Unlisted, fed-back outputs are interpreted as nodes in the top-level source following the naming convention: instance_name/node_name
Bidirectional | Listing bidirectional signals is optional, except for those with output enable (OE). If you specify bidirectional signals, the compiler checks for invalid wire connections.

Caution! Interface declarations cannot contain dot extensions. If you need a specific dot extension across a source boundary (to resolve feedback ambiguities, for example), you must introduce an intermediate signal into the lower-level source to provide the connection to the top-level source. All dot extension equations for a given output signal must be located in the ABEL-HDL source in which the signal is defined. No references to that signal's dot extensions can be made outside of the ABEL-HDL source.

Note When you instantiate a lower-level source in a top-level source, any signal attributes (explicit or implicit) are inherited by the top-level source signals that map to the lower-level signals. Do not specify ISTYPEs for instantiated signals.

Unlisted Signals

If you do not list some signals of the lower-level module in the interface statement, the following rules apply:

Unlisted Pins Are: | The Compiler Interprets Them As:
Inputs or Bidirectionals with OE | Errors
Outputs | No Connects (NC), and they can be removed
Feedback outputs | Nodes in the top-level source, following the naming convention: instance_name/node_name

Example

The following interface statement declares inputs ce, ar, and clk, (giving default values for two of them) and outputs q3 through q0.

module cnt4 interface (ce=1,ar=1,clk -> [q3..q0]) ;

Specifying default values allows you to instantiate cnt4 without declaring the ce and ar inputs in the top-level source. If you do not declare these inputs, they are replaced with the constants 1 and 0, respectively. Since these constants may affect the optimization, you may need to re-optimize the lower-level source with the constants.

Note Supported default values are 1, 0, or X (don't care). You can give default values for a set with a positive integer, and each digit of the integer's binary form supplies the default value for the corresponding signal in the set.


TITLE

Title Keyword

Syntax

TITLE 'string'

Use

The title statement is used to give a module a title that will appear as a header in both the programmer load file and documentation file created by the language processor. The title is specified in the string following the keyword, TITLE. The string is opened and closed by an apostrophe. The title statement is optional.

Example

An example of a title statement that spans three lines and describes the logic design is shown below:

module m6809a
title '6809 memory decode, Jean Designer
Xilinx'


Invert/Buffer Example

The test vectors in the following two designs illustrate how the 'invert' attribute complements output signals with detailed dot extensions (.D, .T, .S, .R., .J., and .K).

module buffer
q0,q1 pin istype 'reg,buffer';
clock pin;
reset pin;

equations
[q1,q0].clk = clock;
[q1.D,q0.D] = [q1.Q,q0.Q] + 1;
[q1.SR,q0.SR] = reset;

test vectors
([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 1 ]->[ 0, 0];
end

module invert
q0,q1 pin istype 'reg,invert';
clock pin;
reset pin;

equations
[q1,q0].clk = clock;
[q1.D,q0.D] = ([q1.Q,q0.Q] + 1);
[q1.SR,q0.SR] = reset;

test vectors
([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 1, 1];
[ .c., 0 ]->[ 1, 0];
[ .c. , 0 ]->[ 0, 1];
[ .c. , 0 ]->[ 0, 0];
[ .c. , 0 ]->[ 1, 1];
[ .c. , 0 ]->[ 1, 0];
[ .c. , 1 ]->[ 1, 1];
end

The 'invert' declaration in the second design results in inverted outputs and in an inverted reset function.


Istype 'invert' and 'buffer'

Using Istype 'invert' and 'buffer'

The istype 'invert' declaration ensures an inverter between the signal's output pin and its associated flip-flop. The istype 'buffer' declaration ensures no inverter between the flip-flop and pin. These attributes are primarily used to control the behavior of presets, resets, and power-up states for devices with programmable output pin inversion, and to restrict device independent designs to certain classes of parts (only those with inverted outputs, for example).

An output can be declared as type 'invert', and still be implemented with either positive or negative-polarity. This is because many devices (such as the P16V8, P16RP4, and others) feature fixed inverters between the flip-flop outputs and the actual output pins, and programmable-polarity elements located at the terminus of the programmable arrays (before the flip-flops). Devices such as this allow automatic polarity selection to be performed (to reduce product term requirements) without affecting the behavior of flip-flops (as observed on the device outputs).

Since the 'invert' and 'buffer' attributes are related to flip-flops, they have no meaning and do not apply to signals that are used or declared as combinational (for example, by using the 'COM' attribute), nor do they apply to input signals.

When 'invert' or 'buffer' are used for an output signal, the information is passed to later ABEL programs (such as the PLASim simulator, device fitters, and the Fuseasm fuse mapper) in the OPEN-ABEL file. If the 'invert' attribute is specified, outputs that were described using the dot extensions .D, .T, .S, .R., .J., and .K are complemented in the programmed device.

To see two designs that illustrate this concept, click on "Invert/Buffer Example" below.

Invert/Buffer Example

The .Q dot extension (for feedback specification) is directly affected by the 'invert' and 'buffer' attributes. When 'invert' is specified, the .Q feedback reference is always the complement of the .FB feedback reference. When 'buffer' is specified, .Q and .FB feedback references are synonymous.


Istype 'buffer' - Non-inverter attribute

Istype 'buffer'
Non-inverter attribute

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'buffer' ;

Use

Signal attribute 'buffer,' (along with its counterpart, 'invert,' to control output inversion) enforces the existence or non-existence of a hardware inverter at the device pin associated with the specified output signal. This is important because the state of the inverter affects a register's reset, preset, preload, and powerup behavior (as observed on the associated output pin).

The 'buffer' attribute indicates that the target architecture does not have an inverter between the associated flip-flop (if any) and the actual output pin.

Note The XC9500 family does not have inverters between the macrocell flip-flop and the output pin.

Example

q0,q1,q2 pin istype 'buffer';
a0,a2 istype 'buffer';


Istype 'collapse' - Collapse Combinational Node Attribute

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'collapse' ;

Use

Signal attribute 'collapse' indicates that this combinational node can be collapsed (removed) by both the ABEL compiler and the Xilinx CPLD fitter. The opposite attribute is ISTYPE 'keep'.

Example

In the following example, signal b is given the 'collapse' attribute:

module coll_b
a,c,d,e pin ;
b pin istype 'collapse'

equations
a = b & e;
b = c & d;

end

The resulting equation collapses b out of the equations:

a = c & d & e ;


Istype 'com' - Combinational Signal Attribute

Istype 'com'
Combinational Signal Attribute

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'com' ;

Use

Signal attribute 'com' is used to specify that a signal has no register element associated with it or that any register should be bypassed.


Istype 'dc' - Unspecified Logic is Don't Care

Istype 'dc'
Unspecified Logic is Don't Care

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'com' ;

Use

Signal attribute 'dc' is used to specify that unspecified logic should be given a value of don't care.

The 'dc' attribute is equivalent to the @DCSET directive, except that it operates on individual signals instead of on an entire section of a design.

Note 'dc,' 'neg,' and 'pos' are mutually exclusive.

Caution: The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.


Istype 'invert' - Inverter Attribute

Istype 'invert'
Inverter Attribute

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'invert' ;

Use

Signal attribute 'invert', along with its counterpart, 'buffer,' controls output inversion, enforcing the existence or non-existence of a hardware inverter at the device pin associated with the specified output signal.

In registered devices, the 'invert' attribute ensures that an inverter will be located between the output pin and its associated register output. This is important because the location of the inverter affects a register's reset, preset, preload, and powerup behavior (as observed on the associated output pin).

Note The XC9500 family does not have inverters between the macrocell flip-flop and the output pin. However, the existance of an inverter is emulated for register behavior that is defined with detailed dot extensions.


Istype 'keep' - Do Not Collapse Signal

Istype 'keep'
Do Not Collapse Signal

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'keep' ;

Use

Signal attribute 'keep' indicates that the combinational node should not be collapsed (removed) by either the ABEL compiler or the Xilinx CPLD fitter.


Istype 'neg' - Unspecified Logic is 1

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'neg' ;

Use

Signal attribute 'neg' indicates that unspecified logic should be given the value of 1.

Note The 'neg' or 'pos' attribute is implied if a device is specified. For example, 'neg' is implied if the device output is inverted (for example, with a 16L8).

Caution: The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.

Note 'dc,' 'neg,' and 'pos' are mutually exclusive.


Istype 'pos' - Unspecified Logic is 0

Istype 'pos'
Unspecified Logic is 0

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'pos' ;

Use

Signal attribute 'pos' indicates that unspecified logic should be given the value of 0.

Note The 'neg' or 'pos' attribute is implied if a device is specified. For example, 'pos' is implied if the device output is not inverted.

Caution: The @DCSET directive overrides 'dc,' 'neg,' and 'pos'.

Note 'dc,' 'neg,' and 'pos' are mutually exclusive.


Istype 'reg' - Clocked Memory Element

Istype 'reg'
Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg' ;

Use

Signal attribute 'reg' indicates that the associated signal has a D-type flip-flop as its memory element. Since flip-flop types are normally determined by the use of ':=' or by the use of dot extensions (.D, .T, etc.) in equations, the 'reg' attribute is only significant when state diagrams are used. When 'reg' is specified, the equations resulting from an ABEL-HDL state diagram will be pin-to-pin registered equations (the same as if you had written equations using ':='). You do not need to worry about the existence of inverted output pins.


Istype 'reg_D' - D Flip-flop Clocked

Istype 'reg_D'
D Flip-flop Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_d' ;

Use

Signal attribute 'reg_d' indicates that the associated signal has a D-type flip-flop as its memory element. When 'reg_D' is specified, equations generated from an ABEL-HDL state diagram will assume a D-type register. If this attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures. To eliminate the need for the 'invert' or 'buffer' attributes, use the 'reg' attribute instead of 'reg_D'.


Istype 'reg_G' - D Flip-flop Gated Clock Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_g' ;

Use

Signal attribute 'reg_G' indicates that the associated signal has a D-type flip-flop with enabled clock as its memory element. Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_g' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.

This register type is emulated in Xilinx CPLDs by multiplexing the flip-flop data input and Q feedback, as selected by the clock enable input.


Istype 'reg_JK' - JK Flip-flop Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_jk' ;

Use

Signal attribute 'reg_jk' indicates that the associated signal has a JK-type flip-flop as its memory element. Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_jk' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.


Istype 'reg_SR' - SR Flip-flop Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_sr' ;

Use

Signal attribute 'reg_sr' indicates that the associated signal has an SR-type flip-flop as its memory element. Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_sr' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.


Istype 'reg_T' - T Flip-flop Clocked Memory Element

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_t' ;

Use

Signal attribute 'reg_t' indicates that the associated signal has a T-type flip-flop as its memory element. Equations generated from an ABEL-HDL state diagram will assume this register type if the 'reg_t' attribute is specified; however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures.


Istype 'retain' - Do Not Minimize This Output

Istype 'retain'
Do Not Minimize This Output

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'retain' ;

Use

Signal attribute 'retain' indicates that redundant product terms for this signal should be retained. The 'retain' attribute only controls optimization performed in the ABEL compiler and in the Xilinx CPLD fitter.


Istype 'xor' - XOR Gate in Target Device

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'xor' ;

Use

Signal attribute 'xor' indicates that the target architecture has an XOR gate, so one top-level exclusive-OR operator is retained in the design equations.


Istype Attributes Overview

Istype Attributes for CPLD Designs - Overview

Attribute | Description | Xilinx Support
'buffer' | Non-inverted signal. | Directly Supported
'collapse' | Collapse (remove) this signal. | Directly Supported
'com' | Combinational signal. | Directly Supported
'dc' | Unspecified logic is don't care. | Directly Supported
'default_0' | Register initializes to "0" | Affects only simulation
'default_1' | Register initializes to "1" | Affects only simulation
'invert' | Inverted signal. | Directly Supported
'keep' | Do not collapse this signal from equations. | Directly Supported
'neg' | Unspecified logic is 1. | Directly Supported
'pos' | Unspecified logic is 0. | Directly Supported
'reg' | Registered output signal. | Directly Supported
'reg_D' | Registered output signal for D Flip-flop. | Directly Supported
'reg_G' | Registered gated clock memory element. | Emulated
'reg_JK' | JK-type registered output signal. | Emulated
'reg_L' | Transparent latch output signal. | Directly supported for CoolRunners, Emulated for XC9500s.
'reg_SR' | SR-type registered output signal. | Emulated
'reg_T' | T-type registered output signal. | Directly Supported
'retain' | Do not minimize output. Preserve redund. prod. terms. | Directly Supported
'xor' | XOR gate | Directly Supported


Istype Keyword

Syntax

signals [PIN | NODE] numbers ISTYPE 'attr';

signal: A pin or node identifier.

number: Optional pin or node numbers.

attr: A string that specifies attributes for the signals, separated by commas.

Use

The ISTYPE statement defines attributes (characteristics) of signals (pins and nodes). You should use signal attributes to remove ambiguities in architecture-independent designs. Even when you have specified a device, using attributes ensures that the design operates consistently if the device is changed later.

You can combine a pin or node declaration with an ISTYPE statement in a single declaration. Supported attributes are listed below.

Example

F0, A pin istype 'invert, reg' ;

This declaration statement defines F0 and A as inverted D-type flip-flops. The following signal declarations are all supported:

q3,q2,q1,q0 NODE ISTYPE 'reg_SR';
Clk,a,b,c PIN 1,2,3,4;
reset PIN;
reset ISTYPE 'com';
Output PIN 15 ISTYPE 'reg,invert';


Istype Keywords

Istype Keywords for CPLD Designs


Istype 'default_0'

This istype keyword is not supported for Xilinx CPLD designs.


Istype 'default_1'

This istype keyword is not supported for Xilinx CPLD designs.


Istype 'reg_L'

Istype 'reg_L' L Flip-flop Clocked Memory Element

Purpose

Signal attribute 'reg_L' indicates that the associated signal has an L-type flip-flop as its memory element. When 'reg_L' is specified, equations generated from an ABEL-HDL state diagram will assume an L-type register. If this attribute is specified, however, you will need to specify the 'invert' or 'buffer' attribute to ensure consistent operation in different architectures. To eliminate the need for the 'invert' or 'buffer' attributes, use the 'reg' attribute instead of 'reg_L'.

Syntax

signal_name [,signal_name] [PIN|NODE] ISTYPE 'reg_l' ;


Karnaugh Map of @Dcset Example

Expressed as a Karnaugh map, the on-set, off-set and dc-set would appear as follows (with ones indicating the on-set, zeroes indicating the off-set, and dashes indicating the dc-set):

\ i1 i0
i3 i2\
\ 00 01 11 10
\---------------
00 | 0 | 0 | 0 | - |
|---|---|---|---|
01 | - | - | 1 | - |
|---|---|---|---|
11 | 1 | - | 1 | 1 |
|---|---|---|---|
10 | 0 | - | - | - |
--- --- --- ---


ABEL-HDL Source Structure

This section provides the basic syntax and structure of an ABEL-HDL design description. For information on specific elements, refer to the Language Reference.

Create your ABEL-HDL source using the Xilinx Foundation HDL Editor. If your ABEL file is used as a top-level design, its file name must be the same as your Foundation project name.

Introduction to ABEL-HDL

Arguments and Argument Substitution

Basic Syntax

Comments

Constants

Dot Extensions

Equation Blocks

Expressions

Hierarchy

Operators

Sample Module

Sets

Set Indexing


LDG Extension

Here is a simple design that illustrates the usage of the .LDG extension:

MODULE ldg_ex1

d1..d0 PIN;

d_internal1..d_internal0 NODE ISTYPE 'REG_L';

my_dgate PIN;

q10 PIN;

d = [d1..d0];

d_internal = [d_internal1..d_internal0];

EQUATIONS

d_internal.D = d;

d_internal.LDG = my_dgate;

q10 = (d_internal == ^H3);

test_vectors([d1, d0, my_dgate ] -> [q10]);

[ 0, 0, 0 ] -> [0];

[ 0, 1, 0 ] -> [0];

[ 1, 0, 0 ] -> [0];

[ 1, 1, 0 ] -> [1];

[ 1, 1, 1 ] -> [1];

[ 0, 1, 1 ] -> [1];

[ 1, 0, 1 ] -> [1];

[ 0, 0, 1 ] -> [1];

[ 0, 0, 0 ] -> [0];

END

Note The only allowed dot extensions associated with a DataGATE latch are .LDG and .D. Dot extensions for resets/presets/clock enables are not allowed in conjunction with a DataGATE latch. This will prevent the user from creating a G_LDG instance with more than the 3 ports defined for that element.

Note Functional simulation of the .LDG dot extension is not supported in blifsim.


Library Keyword

Syntax

LIBRARY 'name'

name - A string that specifies the name of the file, excluding the file extension.

Use

The LIBRARY statement causes the contents of the indicated file to be inserted in the ABEL source file. The insertion begins at the point where the LIBRARY statement is located. The file extension of '.inc' is appended to the name specified, and the resulting file name is searched for. If no file is found, ABEL will attempt to find the file in the abel5lib.inc library file.


Logical Operators

Logical operators are used in expressions. ABEL-HDL incorporates the standard logical operators listed below. Logical operations involving operands of more than one bit are performed bit by bit. For alternate operators, refer to the @Alternate directive.

Operator | Result | Description
! | NOT: ones complement | exclamation point
& | AND | ampersand
# | OR | pound sign
$ | XOR: exclusive OR | dollar sign
!$ | XNOR: exclusive NOR | exclamation point/dollar sign


Macro Keyword

Syntax

macro_id MACRO [ ( dummy_arg[,dummy_arg]... ) ] {block} ;

macro_id - An identifier naming the macro.

dummy_arg - A dummy argument.

block - A block.

Use

The macro declaration statement defines a macro. You can use macros to include ABEL code in a source file without typing or copying the code everywhere you need it. A macro is defined once in the declarations section of a module and then used anywhere within the module as frequently as needed. Macros can be used only within the module in which they are declared.

Example

The dummy arguments used in the declaration of the macro allow different actual arguments to be used in the macro each time it is invoked in the module. Within the macro, dummy arguments are preceded by a "?" to indicate that an actual argument will be substituted for the dummy by the ABEL compiler.

D = NAND3 (Clock,Hello,Busy) ;

brings the text in the block associated with NAND3 into the code, with Clock substituted for ?A, Hello for ?B, and Busy for ?C. This results in

D = ! ( Clock & Hello & Busy ) ;

which is the three input NAND.


Memory Address Decoder

The following design illustrates address decoding, which is a typical application of programmable logic devices.

Design Specification

The following figure shows the block diagram for this design and a continuous block of memory divided into four sections containing DRAM, I/O, ROM1 and ROM2. The purpose of this decoder is to monitor the six high-order bits (A15-A10) of a sixteen-bit address bus and select the correct section of memory based on the value of these address bits.

The address ranges associated with each section of memory are shown as follows. These address ranges can also be seen in the source file.

Memory Section | Address Range (Hex)
DRAM | 0000-DFFF
I/O | E000-E7FF
ROM2 | F000-F7FF
ROM1 | F800-FFFF

Design Method

The following figure shows a simplified block diagram for the address decoder. The decoder is implemented with equations employing relational and logical operators as shown in the Memory Address Decoder Source File below.

Significant simplification is achieved by grouping the address bits into a set named Address. The ten address bits that are not used for the address decode are given no-connect values in the set, indicating that the address in the overall design (that beyond the decoder) contains 16 bits, but that bits 0-9 do not affect the decode of that address and are not monitored. In contrast, defining the set as:

Address = [A15,A14,A13,A12,A11,A10]

ignores the existence of the lower-order bits. Specifying all 16 address lines as members of the address set allows full 16-bit comparisons of the address value against the ranges above.

Test Vectors

In this design, the test vectors are a listing of the values that must appear on the output lines for specific address lines for specific address values. The address values are specified in hexadecimal notation.

Memory Address Decoder Source File

module decode

title 'memory decode Xilinx'

A15,A14,A13,A12,A11,A10 pin 1,2,3,4,5,6;

ROM1,IO,ROM2,DRAM pin 14,15,16,17 istype 'com';

H,L,X = 1, 0, .X. ;

Address = A15,A14,A13,A12, A11,A10,X,X, X,X,X,X, X,X,X,X;

equations

!DRAM = (Address <= ^hDFFF);

!IO = (Address >= ^hE000) & (Address <= ^hE7FF);

!ROM2 = (Address >= ^hF000) & (Address <= ^hF7FF);

!ROM1 = (Address >= ^hF800);

test_vectors

(Address -> [ROM1,ROM2,IO,DRAM])
^h0000 -> [ H, H, H, L ];
^h4000 -> [ H, H, H, L ];
^h8000 -> [ H, H, H, L ];
^hC000 -> [ H, H, H, L ];
^hE000 -> [ H, H, L, H ];
^hE800 -> [ H, H, H, H ];
^hF000 -> [ H, L, H, H ];
^hF800 -> [ L, H, H, H ];

end


Message Types

Messages fall into the following categories:

Message Type | Indication
Logical Error | A problem with the design logic.
Device File Error | A problem with the device selected.
Internal Error | A program functional error.
License Error | A problem with the license manager or license file.
Note | Information.
Fatal Error | A process could not continue or is waiting for additional input.
Command Line Error | Unrecognized use of the command line.
Syntax Error | Unrecognized use of ABEL-HDL.
Warning | Design changes have been made that may affect the functionality of the design, but processing has not been interrupted.


Mixed Pin-to-pin and Detailed Example

In this example, pin-to-pin and detailed descriptions are combined: the reset function is described using detailed design methods, and the rest of the circuit is described pin-to-pin.

module count
q0,q1 pin istype 'reg,buffer';
clock pin;
reset pin;
equations
[q1,q0].clk = clock;
[q1,q0] := [q1.FB,q0.FB] + 1;
[q1.SR,q0.SR] = reset;
test vectors ([clock,reset]->[q1,q0])
[ .c. , 1 ]->[ 0, 0];
:
end

Note When you describe a preset or reset function with a detailed description, you need to include an 'invert' or 'buffer' attribute. If you specify 'invert', the preset logic is reversed (and acts as a reset when observed from the pin).


Module Keyword

Syntax

MODULE modname [ ( dummy_arg [,dummy_arg] ... ) ]

modname - A valid identifier naming the module.

dummy_arg - A dummy argument.

Use

The module statement defines the beginning of a module and must be paired with an END statement that defines the module's end.


Command Error 1000

Command Error 1000: You must specify an ABEL-HDL source file.

An ABEL-HDL source file is expected as the input for compilation by the compiler. From the menus, the active window is processed. On the command line, the file should be specified as the first argument to the compiler.


Error 1001

Command Line Error 1001: An Open-ABEL 2 file must be specified.

The Open-ABEL Report Generator is expecting an input file that is in Open-ABEL 2.0 format.

Fatal Error 1001: File name is too long.

The specified input filename exceeds the number of characters supported by your computer's operating system.


Fatal Error 1002

Fatal Error 1002: Input and output file are the same.

Input and output filenames must be unique. A specified input filename is identical to the output filename. Respecify either the input or output filename.


Fatal Error 1003

Fatal Error 1003: Unable to open input file 'XXX'.

The input file specified cannot be found or read. Make sure that the input file is on the specified path and is in Open-ABEL 2 format.


Fatal Error 1004

Fatal Error 1004: Unable to open output file 'XXX'.

Your computer's operating system cannot create the specified output file.


Syntax Error 1005

Syntax Error 1005: Identifier length exceeds ## chars.

Identifiers (module, device, signal and constant names) must not exceed the indicated length.


Syntax Error 1006

Syntax Error 1006: Undefined token

An unrecognized sequence of non-alphabetic characters was encountered in the source file.


Syntax Error 1007

Syntax Error 1007: String length exceeds ## chars.

A string was encountered that exceeds the maximum supported number of characters. This is usually an indication that the terminating string delimiter was unintentionally omitted.


Syntax Error 1008

Syntax Error 1008: Only ^b, ^o, ^d or ^h radix supported.

The ^ (circumflex) character was encountered in the source file with an unknown radix character immediately following it.


Syntax Error 1009

Syntax Error 1009: Can't have letters imbedded in a number.

A sequence of numeric and alphabetic characters was encountered in the source file to be used as a number.


Logical Error 1010

Logical Error 1010: Numeric overflow

An operation performed on constant values resulted in a number larger than supported.


Syntax Error 1011

Syntax Error 1011: Actual argument length exceeds 35 chars.

An actual argument (the text passed as an argument to a macro or module) exceeds the indicated maximum number of characters.


Syntax Error 1012

Syntax Error 1012: No more than nn arguments are declared.

The macro or module being processed has only the indicated number of dummy arguments declared, and the macro or module was called with too many actual arguments.


Warning 1013

Warning 1013: Attribute 'FEED_OR' is obsolete - substituting '.D' instead.

The 'FEED_OR' signal attribute was used in previous versions of the compiler to specify the feedback configuration for the indicated signal. In ABEL-HDL, the feedback path is specified as a part of the related design description by using dot extensions. The appropriate dot extension to indicate the combinational feedback path from a registered output is typically '.D', so this dot extension will be appended to all affected signals when they are referenced as inputs.


Warning 1014

Warning 1014: Attribute 'FEED_PIN' is obsolete - substituting '.PIN' instead.

The 'FEED_PIN' signal attribute was used in previous versions of the compiler to specify the feedback configuration for the indicated signal. In ABEL-HDL, the feedback path is specified as a part of the related design description by using dot extensions. The appropriate dot extension to indicate the feedback path from an output pin is '.PIN', so this dot extension will be appended to all affected signals when they are referenced as inputs.


Warning 1015

Warning 1015: Attribute 'FEED_REG' is obsolete - substituting '.FB' instead.

The 'FEED_REG' signal attribute was used in previous versions of the compiler to specify the feedback configuration for the indicated signal. In ABEL-HDL, the feedback path is specified as a part of the related design description by using dot extensions. The appropriate dot extension to indicate the registered feedback path is typically '.FB', so this dot extension will be appended to all affected signals when they are referenced as inputs.


Fatal Error 1016

Fatal Error 1016: Unable to open output file 'xxxx'.

The indicated file could not be opened. This can indicate a full disk drive, invalid path, or file protection problems.


Syntax Error 1017

Syntax Error 1017: ENDCASE expected

The CASE transition statement must be terminated with an ENDCASE statement.


Syntax Error 1018

Syntax Error 1018: No register type specified for 'xxxx' - please use ISTYPE.

The indicated signal has not been declared with a register type. If no device and pin number have been declared, you should use the ISTYPE statement to specify that the signal is either combinational (ISTYPE 'COM') or registered (ISTYPE 'REG' or ISTYPE 'REG_X' where X is either D, T, SR, JK, JKD or G).


Syntax Error 1019

Syntax Error 1019: Keyword 'xxxx' expected

The indicated keyword was expected in the source file.


Syntax Error 1020

Syntax Error 1020: Identifier name expected.

An identifier (module, device, signal or constant name) was expected in the source file but not found.


Syntax Error 1021

Syntax Error 1021: Undefined compiler directive '@xxxx'.

An '@' sign was encountered that was followed by an unknown directive name.


Syntax Error 1022

Syntax Error 1022: Special constant must end with a '.'.

Special constants are delimited by '.' (period) characters. This Error can also indicate incorrect usage of dot extensions, which are prefixed by '.' characters.


Syntax Error 1023

Syntax Error 1023: Undefined special constant 'xxxx'.

An unknown special constant was found delimited by '.' (period) characters.


Syntax Error 1024

Syntax Error 1024: Identifier name expected.

An identifier (module, device, signal or constant name) was expected in the source file but not found.


Syntax Error 1025

Syntax Error 1025: Can't use ':=' operator with dot extension signal 'xxxx'.

The ':=' (registered assignment) operator is used to indicate a pin-to-pin relationship between an input expression and a corresponding registered output pin. Dot extension signals are inherently combinational, and should therefore be described with the '=' (unclocked assignment) operator.


Syntax Error 1026

Syntax Error 1026: ';' expected

A semicolon was expected in the source file.


Syntax Error 1027

Syntax Error 1027: Module name doesn't match 'xxxx'.

The END statement was followed by a module name that does not match the module name specified in the previous MODULE statement.


Syntax Error 1028

Syntax Error 1028: EQUATIONS, STATE_DIAGRAM, TRUTH_TABLE or END expected.

A keyword was encountered out of place in the source file. This can indicate any number of syntax problems, including misplaced or missing semicolons or parenthesis, unbalanced IF-THEN, WHEN-THEN or CASE statements, or earlier syntax problems.


Syntax Error 1029

Syntax Error 1029: PIN, NODE, DEVICE, ISTYPE, MACRO or '=' expected.

A label, keyword or operator was encountered out of place in the declarations section of the source file. This error often results if a comma is omitted from a list of identifiers.


Warning 1030

Warning 1030: Inconsistency in number of parameters - declaration ignored.

A constant declaration statement had an unbalanced number of items on the right and left side of the '=' (constant assignment) operator.


Syntax Error 1031

Syntax Error 1031: Undefined identifier 'xxxx'.

An identifier was referenced that was not declared in a declarations section of the source file.


Syntax Error 1032

Syntax Error 1032: Signal not supported.

A signal is not allowed as an operand or argument in the indicated expression.


Syntax Error 1033

Syntax Error 1033: Max of nn elements in set was exceeded.

Set widths are restricted to 128 elements.


Syntax Error 1034

Syntax Error 1034: ']' expected

A set was not terminated with a ']' (right bracket) delimiter character.


Syntax Error 1035

Syntax Error 1035 : Illegal operation on special constant.

Special constants are not allowed as operands in the indicated expression.


Syntax Error 1036

Syntax Error 1036: Can't compare set with nn members to one with nn members.

Set widths must match when performing operations on two sets.


Syntax Error 1037

Syntax Error 1037: ')' expected

The ')' (right parenthesis) character was expected as a delimiter.


Syntax Error 1038

Syntax Error 1038: Pin number, ISTYPE or semicolon expected.

A signal (PIN or NODE) declaration was not properly terminated.


Syntax Error 1039

Syntax Error 1039: Identifier name 'xxxx' is already defined.

The indicated identifier name was used in a previous declaration. This indicates a missing or misplaced EQUATIONS keyword.


Syntax Error 1040

Syntax Error 1040: Number expected

A number was expected in the source file. Numbers can be prefixed by a radix specification, or can be specified as a set of binary values.


Syntax Error 1041

Syntax Error 1041: Keyword 'xxxx' is out of context.

The indicated keyword was used in an incorrect manner.


Logical Error 1042

Logical Error 1042: Premature end of source file.

The end of the source file was encountered before an END statement was found.


Warning 1043

Warning 1043: ':=' should not be used with output type 'xxxx'.

The ':=' (clocked assignment) operator is intended for use with D-type flip-flops only. For alternate flip-flop types, you should use the '=' (combinational assignment) operator in conjunction with either a '.T', '.J', '.K', '.S', '.R', or other register input port dot extension.


Syntax Error 1044

Syntax Error 1044: Device identifier name expected.

The compiler expects a device filename to continue processing. Specify a device filename.


Warning 1045

Warning 1045: 'INVERT' or 'BUFFER' not specified for 'xxxx' - output uncertain.

An output signal has been described using a register input port dot extension ('.D', '.T', '.J', '.K', '.S', or '.R') but the associated output signal has not been declared with an 'INVERT' or 'BUFFER' attribute. Since there is no information about the existence of an inverter between the register and the associated output pin, the actual value observed on that pin is uncertain.


Syntax Error 1046

Syntax Error 1046: Cannot operate on signal 'xxxx'.

The indicated signal was used in an expression in which only numbers or constant values are allowed.


Syntax Error 1047

Syntax Error 1047: Signal or .X. expected

A declared signal (pin or node) or the special constant '.X.' was expected in the source file.


Syntax Error 1048

Syntax Error 1048: '=' or ':=' expected

An assignment operator was expected in the source file.


Syntax Error 1049

Syntax Error 1049: Expression element expected

An expression was expected in the source file. Expressions are composed of one or more signals, sets, numbers or special constants operated on by valid ABEL-HDL operators. Expressions may or may not be enclosed in a pair of parenthesis.


Warning 1050

Warning 1050: 'INVERT' or 'BUFFER' not specified for 'xxxx' - feedback uncertain.

Feedback from a registered signal has been described using the '.Q' dot extension, but the associated output signal has not been declared with an 'INVERT' or 'BUFFER' attribute. Since there is no information about the existence of an inverter between the register and the associated output pin, the relationship between the value observed on that pin and the value fed back from the register is uncertain.


Syntax Error 1051

Syntax Error 1051: GOTO, IF or CASE expected

A state transition (GOTO, IF-THEN-ELSE, or CASE) statement was expected.


Syntax Error 1052

Syntax Error 1052: THEN expected

The THEN portion of an IF-THEN-ELSE statement was omitted.


Syntax Error 1053

Syntax Error 1053: Signal 'xxxx' is combinational.

The ':=' (clocked assignment) operator was used to describe a signal that was declared as combinational.


Syntax Error 1054

Syntax Error 1054: '(' expected

A '(' (left parenthesis) character was expected as a delimiter.


Syntax Error 1055

Syntax Error 1055: '->' expected

The '->' operator was expected to delimit the input and output portions of a truth table or test vector header or entry.


Logical Error 1056

Logical Error 1056: Extension 'XXX' is not legal for node 'XXX'.

The indicated dot extension is not supported by the indicated node.


Syntax Error 1057

Syntax Error 1057: Can't map set onto a non-set element.

A set was specified in a test vector where a single-bit value was expected.


Syntax Error 1058

Syntax Error 1058: Special constant not allowed.

Special constants are not allowed in the current context.


Syntax Error 1059

Syntax Error 1059: Undefined operation on sets.

Sets may not be used as operands of '>>' (shift right), '<<' (shift left), '*' (multiply), '/' (divide) or '%' (modulo) operators.


Syntax Error 1060

Syntax Error 1060: Can't map set onto a different sized set

Set widths must match when performing operations on two sets, or when using nested sets in truth tables or test vectors.


Warning 1061

Warning 1061: No output type specified for 'xxxx' - please use ISTYPE.

You have used the indicated signal as an output, but have not declared whether it is combinational or registered.


Warning 1062

Warning 1062: Extension 'xxxx' may not be legal for signal 'xxxx'.

You have used a dot extension that does not match the known dot extensions for the output type declared for the indicated signal.


Syntax Error 1063

Syntax Error 1063: Dummy argument 'xxxx' not recognized.

You have indicated a dummy argument (by prefixing a label with the '?' character) that does not match the dummy arguments declared in the macro or module argument list.


Syntax Error 1064

Syntax Error 1064: Signal number for 'xxxx' is too large.

You have specified a very large pin or node number.


Syntax Error 1065

Syntax Error 1065: Pin or node number 'XXX' is not defined for this device.

You have specified a pin or node that is undefined for the declared device.


Syntax Error 1066

Syntax Error 1066: Node number nn is not defined for this device.

You have specified a node number that is undefined for the declared device.


Syntax Error 1067

Syntax Error 1067: Only one name allowed for each macro.

You have specified a list of names in a macro definition. Only one name is allowed for each macro.


Syntax Error 1068

Syntax Error 1068: Block expected

A block was expected following a macro keyword or directive. A block is a section of ABEL-HDL source statements enclosed by braces.


Syntax Error 1069

Syntax Error 1069: Closing '}' of block not found.

A terminating '}' (right brace) delimiter was not found in the source file.


Warning 1070

Warning 1070: Pin number nn is already declared as 'xxxx'.

You have declared the same pin number for two different named signals.


Syntax Error 1071

Syntax Error 1071: Closing ' of string not found.

The terminating ' (single quote) character was omitted from a string. This error can occur if a single quote (or back quote) character is imbedded in a string without being prefixed by a '\' (backslash) character.


Syntax Error 1072

Syntax Error 1072: ':+:' or ':*:' expected

You have specified @ALTERNATE (use alternate operators) and have incorrectly specified an XOR or XNOR operation.


Syntax Error 1073

Syntax Error 1073: Constant identifier name expected.

The @CONST directive requires a constant identifier name that has not been previously declared (as a signal, macro or other identifier). It may have been used in a previous @CONST directive.


Syntax Error 1074

Syntax Error 1074: '=' expected

The '=' (assignment operator) was omitted from an @CONST directive or from a fuse assignment statement.


Syntax Error 1075

Syntax Error 1075: Undefined operation on signal.

A signal identifier is not legal in the current context.


Syntax Error 1076

Syntax Error 1076: Number is too large.

Numbers (either literal values or values produced by complex expressions) must not exceed the maximum size of 128 bits (unsigned).


Syntax Error 1077

Syntax Error 1077: ':>' or '->' expected

The ':>' or '->' operator was expected to delimit the input and output portions of a test vector header or entry line.


Syntax Error 1078

Syntax Error 1078: ':>' expected

The ':>' operator was expected in a test vector entry line to match the ':>' operator found in the test vector header.


Syntax Error 1079

Syntax Error 1079: Radix nn is not one of 2, 8, 10 or 16.

The radix value specified in a @RADIX statement must be either 2 (binary), 8 (octal), 10 (decimal) or 16 (hexadecimal).


Syntax Error 1080

Syntax Error 1080: nn actual arguments expected

A macro or module was invoked with an incorrect number of actual arguments.


Syntax Error 1081

Syntax Error 1081: Dummy argument expected

The '?' character indicates that the following sequence of characters is a dummy argument. The error indicates that the dummy argument label does not match any of the dummy arguments listed in the macro or module declaration.


Syntax Error 1082

Syntax Error 1082: Digit not in radix nn.

You have specified a radix value less than 10 (decimal) and have used a digit that is not legal for that number system.


Warning 1083

Warning 1083: Signal 'XXX' is declared as registered.

The indicated signal was declared as a registered output, but was used as a combinational output.


Warning 1084

Warning 1084: Unrecognized attribute 'xxxx' - ignored.

The attribute string specified in an ISTYPE statement was not recognized as a valid signal attribute.


Syntax Error 1085

Syntax Error 1085: 'xxxx' attribute not allowed on this pin.

The specified attribute is not legal for the device and pin or node number indicated, or the attribute conflicts with a previous attribute specified for the same signal.


Warning 1086

Warning 1086: Signal 'XXX' has not been declared as combinatorial.

You have written a combinational function for the indicated signal, but have not specified that the signal is combinational (ISTYPE 'COM').


Warning 1087

Warning 1087: Signal 'xxxx' has not been declared as registered.

You have written a registered (pin-to-pin) function for the indicated signal, but have not declared the signal as registered (ISTYPE 'REG' or ISTYPE 'REG_X' where X is a register type).


Syntax Error 1088

Syntax Error 1088: Symbolic state register name not supported.

Symbolic state names (declared with the STATE_REGISTER declaration) are not supported in the type of expression indicated.


Syntax Error 1089

Syntax Error 1089: 'xxxx' is already defined.

The indicated identifier name was previously declared.


Logical Error 1091

Logical Error 1091: nn actual arguments specified on command line.

The number of actual arguments specified on the Compile Logic command line exceeds the number of dummy arguments specified in the MODULE statement.


Syntax Error 1092

Syntax Error 1092: Use '#' for OR instead of '|'.

The '|' operator (used in some programming languages for a bitwise OR) is not used in ABEL-HDL. Use the '#' operator instead.


Syntax Error 1093

Syntax Error 1093: 'xxxx' undefined, maybe 'xxxx' was meant.

An identifier was encountered that is undefined, but a similar identifier (one that matches if upper and lower case are ignored) exists in the design.


Syntax Error 1094

Syntax Error 1094: No operators allowed in this context.

You have attempted to use a complex expression (one containing operators) when only signals, numbers or special constants are allowed. This error most frequently occurs when dot extensions are applied to complex expressions.


Logical Error 1095

Logical Error 1095: Block or marco nested too far. (Possible mis-use of macro arguments.)

The compiler detects use of a macro argument in a way that is not supported. Refer to the ABEL-HDL Reference for information regarding the supported uses of macro arguments.


Logical Error 1096

Logical Error 1096: Arithmetic error

A divide by zero or similar situation was encountered when evaluating an expression.


Logical Error 1097

Logical Error 1097: Output 'XXX' appears twice in truth table header.

An output of a truth table is represented twice in the truth table's header. Signals should only be represented once on the output side.


Syntax Error 1098

Syntax Error 1098: Negative declaration not allowed.

Negative (active-low) declarations are only allowed in PIN and NODE statements.


Syntax Error 1099

Syntax Error 1099: Invalid set range.

A range (specified with the '..' operator) is bounded by incompatible signals or numbers. Ranges must be specified that will result in 128 or fewer set elements.


Syntax Error 1100

Syntax Error 1100: Bad element 'xxxx' in range.

The expansion of a range expression resulted in the creation of a previously unknown (undeclared) element.


Syntax Error 1101

Syntax Error 1101: Fuse number expected.

A number was expected that corresponds to a fuse location in the declared device.


Syntax Error 1102

Syntax Error 1102: Fuse value 1 or 0 expected.

A fuse value was expected. A value of 0 indicates an intact fuse, and a value of 1 indicates a programmed (blown) fuse.


Syntax Error 1103

Syntax Error 1103: Illegal nested set in state diagram header.

A state diagram state register must be specified as a set of signals, and the set must not be nested (contain other subsets).


Syntax Error 1104

Syntax Error 1104: Dot extension 'xxxx' not legal in this context.

The indicated dot extension is either unrecognized, or used in an unsupported manner. Dot extensions can only be applied to signals or sets of signals.


Syntax Error 1105

Syntax Error 1105: Signal name expected.

An identifier was used that was not a previously declared signal. A signal name was expected.


Syntax Error 1109

Syntax Error 1109: Register type of 'xxxx' does not match other set elements.

State diagrams require matching register types. The state register set specified contains signals of differing register types.


Syntax Error 1110

Syntax Error 1110: Pin nn (VCC) can't be used as input.

You have specified a device and pin number combination that cannot be used as an input in your design.


Syntax Error 1111

Syntax Error 1111: Pin nn (GND) can't be used as input.

You have specified a device and pin number combination that cannot be used as an input in your design.


Syntax Error 1112

Syntax Error 1112: Cannot use .FB or .Q as an output.

The .FB and .Q dot extensions are used for register feedback, and are only supported on the right side of an equation.


Warning 1113

Warning 1113: ENABLE keyword obsolete - use .OE extension instead.

The ENABLE keyword is no longer supported in ABEL-HDL. Instead, you should use the '.OE' dot extension to indicate a three-state output.


Syntax Error 1114

Syntax Error 1114: 'xxxx' attribute not allowed for state registers.

The indicated attribute is illegal for describing state register types. You must specify either 'COM', 'REG', or 'REG_X' where X is a valid register type.


Logical Error 1115

Logical Error 1115: No outputs defined for module 'xxxx'.

An interface statement was encountered that did not contain any output or input/output ports. Use the -> and :> delimiters to specify output and input/output ports, respectively.


Syntax Error 1116

Syntax Error 1116: Multiple attribute list not allowed in this context.

You have used the '=' operator to specify signal attributes for signals that have not been assigned pins. You should use the 'ISTYPE' attribute to assign attributes instead of the '=' operator.


Syntax Error 1117

Syntax Error 1117: State register name expected.

The compiler expects a state register name where indicated by '^'.


Syntax Error 1118

Syntax Error 1118: Module 'module_name' has already been declared.

The indicated submodule has already been declared in an INTERFACE statement, or the identifier has already been defined as some other type of declaration.


Syntax Error 1120

Syntax Error 1120: Only one device allowed.

Multiple device declarations are no longer supported in ABEL-HDL. Instead, you should use the Equation splitter utility to split a large design into multiple devices.


Syntax Error 1121

Syntax Error 1121: Device declaration must be made before signal declarations.

If a device declaration is made in the source file, it must be made before any signal declarations.


Logical Error 1122

Logical Error 1122: File name 'xxxx.xxx' too long.

The indicated file name is too long for the operating system.


Warning 1124

Warning 1124: 'INVERT' or 'BUFFER' not specified for 'xxxx' - assuming 'buffer'.

You have not specified whether the indicated output signal will have an inversion between the state register and the associated output pin. No inversion will be assumed, resulting in possibly incorrect operation if the design is implemented in a device with inverting outputs.


Syntax Error 1125

Syntax Error 1125: 'IN' expected.

The PLACE statement requires that a partition name be specified using the PLACE IN syntax.


Syntax Error 1126

Syntax Error 1126: Can't use ':=' operator with dot extensions.

The ':=' (clocked assignment) operator is used to describe the operation of an registered output pin. If dot extensions are used, you should use the '=' assignment operator, since dot extensions (including register input ports) are inherently combinational.


Syntax Error 1128

Syntax Error 1128: Can't have operators in state register.

The state register set must consist of a set of signals, with no complex operators.


Syntax Error 1129

Syntax Error 1129: Can't expand expression - possibly recursive definition.

The compiler has detected a recursive constant declaration. Check to make sure you have not referenced the same identifier on both sides of the '=' operator.


Syntax Error 1130

Syntax Error 1130: Missing set element.

Set elements can consist of signals, numbers, special constants, sets or expressions and are separated by commas. One of these items was expected in the set.


Syntax Error 1131

Syntax Error 1131: Missing set range element.

The '..' (set range) operator was used with no second boundary element.


Syntax Error 1132

Syntax Error 1132: Keyword IN no longer supported.

Multiple device declarations and corresponding device-specific sections are no longer supported in ABEL-HDL. Instead, you should use the Equation splitter utility to split a large design into multiple devices.


Syntax Error 1133

Syntax Error 1133: Signal 'xxxx' already defined as type 'INVERT'.

You have specified the 'BUFFER' attribute for a signal that was previously declared as 'INVERT'.


Syntax Error 1134

Syntax Error 1134: Signal 'xxxx' already defined as type 'BUFFER'.

You have specified the 'INVERT' attribute for a signal that was already defined as type 'BUFFER'.


Logical Error 1135

Logical Error 1135: 'Port' is an output of 'functional block'.

The indicated signal was declared as an input, but was found on the left side of an equation. This error occurs if an output port of a functional block is used on the left side of an equation.


Logical Error 1136

Logical Error 1136: 'Port' is an input to 'functional block'.

The indicated signal was declared as an output, but was found on the right side of an equation. This error occurs if an input port of a functional block is used on the right side of an equation.


Logical Error 1137

Logical Error 1137: Signal 'xxxx' is type 'bidir'.

The indicated signal was declared as either input or output, but was found on both the right and left side of equations.

Logical Error 1137: The ABEL-HDL Compatibility 'implied' property is not set.

Set the Compile Logic property ABEL-HDL Compatibility to "implied." With this property set to "implied," the ABEL-HDL compiler uses information in the device files to imply attributes or logic for signals that have been assigned to device pins. Press F1 while on the ABEL-HDL Compatibility property for more information.


Warning 1138

Warning 1138: The ABEL-HDL Compatibility 'implied' property is not set.

When you specify a device in an ABEL-HDL source file, you must set the 'implied' property to generate implied logic equations for the device (such as those for a clock) that are necessary to simulate the device.


Warning 1139

Warning 1139: Adding implied 'xxxx' equation for output 'xxxx'.

An equation is being generated for the indicated output due to implied logic (clocks or output enables) in the target device. The use of implied clocks and enables is not recommended; you should add the appropriate clock and enable equations to the design.


Syntax Error 1140

Syntax Error 1140: State machine reset syntax not supported for non-symbolic state diagram.

The SYNC_RESET and ASYNC_RESET statements are only supported in symbolic state diagrams.


Warning 1143

Warning 1143: Sub-module name being converted to lower case (xxx).

To ensure that output filenames are generated correctly, all characters in module and sub-module names that appear in interface statements must be lower-case. All upper-case characters in module names are converted to lower-case characters. The resulting output files contain all lower-case characters.


Syntax Error 1145

Syntax Error 1145: Identifier name 'xxxx' is already declared as a number.

An identifier that is declared as a number was used in a way that is not supported for numbers.


Warning 1146

Warning 1146: Truncating sub-module name to 8 characters (xxx)

Module names can have up to eight characters. The compiler truncates module names that exceed eight characters to continue processing.


Logical Error 1147

Logical Error 1147: Signal 'xxx' does not have an equation or default value.

One of the input ports to a functional block is unconnected. To connect the input of the functional block, write an equation for that port, or add a default value to the module's interface statement.


Warning 1151

Warning 1151: Assuming 'buffer' for dot extension conversion.

A pin-to-pin dot extension is being converted to detailed syntax, but there is no 'invert' or 'buffer' attribute specified. The conversion will be made with the assumption that the output will not be inverted. You should add a 'buffer' or 'invert' attribute to ensure that the design works as expected..


Syntax Error 1152

Syntax Error 1152: Module name expected. Missing interface declaration?

The FUNCTIONAL_BLOCK statement requires a module name that has previously been defined with an INTERFACE statement.


Warning 1153

Warning 1153: Truncating module name to 8 characters ('XXX')

Module names can have up to eight characters. The compiler truncates module names that exceed eight characters to continue processing.


Syntax Error 1154

Syntax Error 1154: Ports of functional blocks are not allowed in test vectors

The compiler does not allow the ports of functional block to be used in test vectors. To monitor the port of a functional block during simulation, you must assign the port to a declared pin or node at the top-level of your hierarchical design.


Syntax Error 1155

Syntax Error 1155: Functional block 'XXX' does not have a port named

The FUNCTIONAL_BLOCK statement requires that a port name be given to the instanced module.


Syntax Error 1158

Syntax Error 1158: Functional block 'XXX' not declared

The functional block being referenced was not declared. All functional blocks must be declared using a 'functional_block' statement.


Syntax Error 1159

Syntax Error 1159: Port 'XXX' has already been defined for interface 'XXX'

A port name can be defined by only one interface statement. Choose another port name to define for the specified interface statement.


Syntax Error 1160

Syntax Error 1160: Set index not supported here (must follow a set or set name)

A set index was used in a place other than after a set or set constant. A set index must immediately follow the set or set constant identifier.


Syntax Error 1161

Syntax Error 1161: Set index not supported for set expression

The set index contained index values that were not supported for the set.


Syntax Error 1162

Syntax Error 1162: '!' expected

A set range was specified with a mismatch of active-level operators.


Syntax Error 1163

Syntax Error 1163: '!' mismatch

A set range was specified with a mismatch of active-level operators.


Syntax Error 1164

Syntax Error 1164: ':' expected

A colon was expected after a state diagram state value or symbolic state identifier.


Fatal Error 1165

Fatal Error 1165: Unable to merge truth table logic for one or more outputs

The compiler does not support the logic for an output to be defined using multiple truth tables. The truth tables for an output must be combined into a single table.


Warning 1166

Warning 1166: Only one XOR factor equation is supported for each output

The compiler only supports one XOR factor equation for each output in the design. Additional XOR factor equations are ignored.


Logical Error 1167

Logical Error 1167: Overlapping logic specified for output 'xxxx'

The indicated output was used as a state diagram state register and conflicting transition logic (non-exclusive IF-THEN logic, for example) was specified.


Logical Error 1168

Logical Error 1168: Incomplete on, off and dc logic specified for output 'xxxx'

Your design specifies on-set, off-set and don't care logic for the indicated output, but the logic is not complete. On-sets are entered using equations, truth tables and state diagrams; off-sets are entered using state diagrams and truth tables, and don't cares are entered using equations. Remove either the on-set, off-set or don't care logic OR enter a complete specification for all three types of logic.


Syntax Error 1169

Syntax Error 1169: Set element type expected for @SETSIZE directive

Enter a set, or the name of a set, in the @SETSIZE directive.


Warning 1170

Warning 1170: No register type specified for 'xxxx' - setting to 'reg'

Your design does not specify a register type for the indicated output, and the output was used in a way that implies a register. Add a register type attribute such as 'reg_D', 'reg_T', to eliminate the warning.


Syntax Error 1171

Syntax Error 1171: No register type specified for state register

A state diagram was written that requires a register type to be specified. Add a register type attribute such as 'reg', 'reg_D', 'reg_T', to eliminate the warning.


Syntax Error 1172

Syntax Error 1172: No state register declared

Your design declares symbolic states using the STATE declaration keyword, but does not declare a state register. Declare a state register before declaring symbolic states.


Syntax Error 1173

Syntax Error 1173: No states declared for 'xxxx'

Your design specifies a state diagram and state register, but does not declare any symbolic state identifiers. Declare the symbolic states using the STATE declaration keyword.


Syntax Error 1174

Syntax Error 1174: Assignment to state register not supported

State registers may only be used with dot extensions such as .CLK (to specify the logic for a state machine clock). A design cannot specify an equation using the symbolic state name as an output. Use a state diagram to define the logic for the state register.


Warning 1178

Warning 1178: Signal 'xxxx' is already 'pos'. Attribute will be overridden

The indicated output has already been assigned an attribute that conflicts with the attribute entered, or design specifies a device and pin number that implies a conflicting attribute. The attribute specified in the design will take precedence.


Warning 1179

Warning 1179: Signal 'xxxx' is already 'neg'. Attribute will be overridden

The indicated output has already been assigned an attribute that conflicts with the attribute entered, or design specifies a device and pin number that implies a conflicting attribute. The attribute specified in the design will take precedence.


Warning 1180

Warning 1180: Signal 'xxxx' is already 'dc'. Attribute will be overridden

The indicated output has already been assigned an attribute that conflicts with the attribute entered, or design specifies a device and pin number that implies a conflicting attribute. The attribute specified in the design will take precedence.


Warning 1181

Warning 1181: Signal 'xxxx' is already 'reg'. Attribute will be overridden

The indicated output has already been assigned an attribute that conflicts with the attribute entered, or design specifies a device and pin number that implies a conflicting attribute. The attribute specified in the design will take precedence.


Warning 1182

Warning 1182: Signal 'xxxx' is already 'com'. Attribute will be overridden

The indicated output has already been assigned an attribute that conflicts with the attribute entered, or design specifies a device and pin number that implies a conflicting attribute. The attribute specified in the design will take precedence.


Fatal Error 2001

Fatal Error 2001: Requires an input file with a .TTn extension

Plaopt requires input files with names such as m6809a.tt1 or foo.tt4. The default output file would be m6809a.tt2 or foo.tt5.


Fatal Error 2002

Fatal Error 2002: Input and output file names are the same 'file_name'

The input and output files must have different names.


Fatal Error 2003

Fatal Error 2003: Can't open input file 'file_name'

Input file not found.


Fatal Error 2004

Fatal Error 2004: AUXPLA and Output file names have the same 'file_name'

The AUXPLA file from the input Equation file has the same name as the output file. The AUXPLA is created when the @DCSET is used in an ABEL-HDL source file.


Fatal Error 2005

Fatal Error 2005: Latte failed on 'file_name'

While producing the @DCSET offsets, the espresso program (latte) was not found or produced an internal error.


Fatal Error 2006

Fatal Error 2006: Can't open input file 'file_name'

While processing the @DCSET, PLAOpt could not open a working file.


Fatal Error 2007

Fatal Error 2007: Can't open AUXPLA file 'file_name'

While processing the @DCSET, PLAOpt could not open the AUXPLA file.


Fatal Error 2008

Fatal Error 2008: Can't open output file 'file_name'

While processing the @DCSET, PLAOpt could not open the output file.


Fatal Error 2009

Fatal Error 2009: Can't open input file 'file_name'

While running '-reduce none', PLAOpt could not open the file.


Fatal Error 2010

Fatal Error 2010: Can't open output file 'file_name'

While running '-reduce none', PLAOpt could not open the file.


Fatal Error 2011

Fatal Error 2011: Latte failed on 'file_name'

While running '-reduce group fixed', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2012

Fatal Error 2012: Latte failed on 'file_name'

While running '-reduce group choose', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2013

Fatal Error 2013: Can't open input file 'file_name'

While running '-reduce group choose', PLAOpt could not open the file.


Fatal Error 2014

Fatal Error 2014: Can't open output file 'file_name'

While running '-reduce group choose', PLAOpt could not open the file.


Fatal Error 2015

Fatal Error 2015: Latte (on-set) failed on 'file_name'

While running '-reduce bypin fixed', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2016

Fatal Error 2016: Can't open input file 'file_name'

While running '-reduce bypin fixed', PLAOpt could not open the file.


Fatal Error 2017

Fatal Error 2017: Can't open output file 'file_name'

While running '-reduce bypin fixed', PLAOpt could not open the file.


Fatal Error 2019

Fatal Error 2019: Latte (on-set) failed on 'file_name'

While running '-reduce bypin choose', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2020

Fatal Error 2020: Latte (off-set) failed on 'file_name'

While running '-reduce bypin choose', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2021

Fatal Error 2021: Can't open input file 'file_name'

While running '-reduce bypin choose', PLAOpt could not open the file.


Fatal Error 2022

Fatal Error 2022: Can't open input file 'file_name'

While running '-reduce bypin choose', PLAOpt could not open the file.


Fatal Error 2023

Fatal Error 2023: Can't open output file 'file_name'

While running '-reduce bypin choose', PLAOpt could not open the file.


Fatal Error 2024

Fatal Error 2024: Latte (on-set) failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2025

Fatal Error 2025: Latte (off-set) failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2026

Fatal Error 2026: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2027

Fatal Error 2027: Design must use D or T flip flops

The PLAOpt design must use the .D or .T detailed equations.


Fatal Error 2028

Fatal Error 2028: Can't open output file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2029

Fatal Error 2029: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2030

Fatal Error 2030: Can't open output file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2031

Fatal Error 2031: Latte failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2032

Fatal Error 2032: Latte failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2033

Fatal Error 2033: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2034

Fatal Error 2034: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2035

Fatal Error 2035: Can't open output file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2036

Fatal Error 2036: Latte failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2037

Fatal Error 2037: Latte failed on 'file_name'

While running '-reduce dt', the espresso program (latte) was not found or produced an internal error.


Fatal Error 2038

Fatal Error 2038: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2039

Fatal Error 2039: Can't open input file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2040

Fatal Error 2040: Can't open output file 'file_name'

While running '-reduce dt', PLAOpt could not open the file.


Fatal Error 2041

Fatal Error 2041: Could not rename 'file_name' to 'file_name'

The file could not be renamed. Check that the file does not exist.


Logical Error 5000

Logical Error 5000: xxx.C and xxx.C have inconsistent modes

Use either asynchronous or synchronous clock through out the design.


Logical Error 5001

Logical Error 5001: xxx pin ## can't be used as output

Reassign pin for the equation with a valid output pin.


Logical Error 5003

Logical Error 5003: xxx pin ## can't be used as input nor feedback

Reassign pin for the input with a valid input/bidir pin.


Fatal Error 5004

Fatal Error 5004: Pin ## is an illegal assignment for xxx

Pin is out of range, try some other device or pin number.


Logical Error 5005

Logical Error 5005: xxx pin ## can't be used as registered output

Reassign pin for the output with a registered pin.


Logical Error 5006

Logical Error 5006: Register of xxx pin ## has no preset

Reassign pin for the output with a registered pin with preset.


Logical Error 5007

Logical Error 5007: Register of xxx pin ## has no reset

Reassign pin for the output with a registered pin with reset.


Logical Error 5008

Logical Error 5008: Register of xxx pin ## has no preload

Reassign pin for the output with a registered pin with preload.


Warning 5009

Warning 5009: Register of xxx pin ## has no asynchronous reset

Part has Synchronous Reset; Reset may not work as expected.


Warning 5010

Warning 5010: Register of xxx pin ## has no synchronous reset

Part has Asynchronous Reset; Reset may not work as expected.


Warning 5011

Warning 5011: Register of xxx pin ## has no asynchronous preset

Part has Synchronous Preset; Preset may not work as expected.


Warning 5012

Warning 5012: Register of xxx pin ## has no synchronous preset

Part has Asynchronous Preset; Preset may not work as expected.


Logical Error 5013

Logical Error 5013: xxx can't be programmed to one-input flip flop of pin ##

Select a device with the specified flip-flop type.


Logical Error 5014

Logical Error 5014: Register of xxx pin ## has no FC line

Select a device with Dynamic Register Control feature.


Logical Error 5016

Logical Error 5016: xxx can't map to pin ##'s [OE | CK]

Check the equation for invalid setting of the macrocell.


Logical Error 5017

Logical Error 5017: xxx.OE is not allowed on pin ##

Select a part with the specified output enable.


Logical Error 5018

Logical Error 5018: xxx can't map to OE of pin ##; only VCC or GND allowed

Select a part with the specified output enable.


Logical Error 5019

Logical Error 5019: xxx can't map to OE of pin ## only pin ## allowed

Modify the OE equation to use the external OE pin.


Logical Error 5020

Logical Error 5020: xxx can't map to OE of pin ##; output is always enabled

Select a part with the specified output enable.


Logical Error 5022

Logical Error 5022: Polarity of pin ##'s OE doesn't match with xxx

Invert the OE equation.


Internal Error 5023

Internal Error 5023: drive_pin(): invalid enable type

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5024

Logical Error 5024: xxx pin ## is not a registered pin

Reassign pin for the output with a registered pin.


Logical Error 5025

Logical Error 5025: Status of xxx register has already been set for this group

Reassign pin for the output with a registered pin.


Logical Error 5027

Logical Error 5027: Register of xxx pin ## can't be bypassed

Reassign pin for the output with a by-passable registered pin.


Internal Error 5028

Internal Error 5028: progTerm(): bad node

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5029

Logical Error 5029: Register type of xxx pin ## is invalid

Try other device with the specified flip flop type.


Logical Error 5030

Logical Error 5030: Dynamic register type of xxx pin ## requires FC equation

Write FC equation to use the dynamic register control.


Logical Error 5031

Logical Error 5031: FC equation of xxx pin ## must be low to use D flip flop

Invert the FC equation.


Logical Error 5032

Logical Error 5032: Dynamic register type of xxx pin ## requires FC equation

Write FC equation to use the dynamic register control.


Internal Error 5033

Internal Error 5033: pregtype(): invalid register type

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5034

Internal Error 5034: Process_IC pSIG for ## is NULL

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5035

Logical Error 5035: xxx pin ## can't be used as feedback

Reassign pin for the feedback for a bidirectional pin.


Logical Error 5036

Logical Error 5036: OR feedback is not allowed on xxx pin ##

Reassign pin for the feedback with pin that has OR feedback.


Logical Error 5037

Logical Error 5037: Registered feedback is not allowed on xxx pin ##

Reassign pin for the feedback with pin that has Q feedback.


Logical Error 5038

Logical Error 5038: Pin feedback is not allowed on xxx pin ##

Reassign pin for the feedback with pin that has pin feedback.


Logical Error 5039

Logical Error 5039: Too many feedbacks are used on xxx pin ##

Check the use of feedbacks in equation with the physical feedback paths.


Logical Error 5040

Logical Error 5040: Only one feedback is allowed on xxx pin ##

Check the use of feedbacks in equation with the physical feedback path.


Internal Error 5041

Internal Error 5041: term_alloc(): PT is null; signum = ##

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5042

Logical Error 5042: xxx can't use XOR on pin ##

Reassign pin for the output with pin that has 2-input XOR gate.


Internal Error 5043

Internal Error 5043: term_alloc(): Pin nn's TT should have been modified

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5044

Logical Error 5044: ## too many terms for output xxx pin ##

Read the Design Consideration chapter in the ABEL-HDL Reference on Polarity Control.


Fatal Error 5045

Fatal Error 5045: Device file not specified

Run fuseasm with -dev device_name; device_name is the targeted device.


Fatal Error 5046

Fatal Error 5046: Invalid pin number assigned to signal xxx

Pin is out of range; try some other device.


Fatal Error 5047

Fatal Error 5047: Can't open file xxx

The file is locked, corrupt or missing.


msg5048

Fatal Error 5048: Unable to close file yyy

There isn't enough space in the directory to open the specified file. Run cleanup4 to erase unnecessary files.


msg5050

Logical Error 5050: Too many terms used by

Read the Design Consideration chapter on Polarity Control in the ABEL-HDL Reference.


Internal Error 5051

Internal Error 5051: Internal error: Pin2MC

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5052

Internal Error 5052: Pin2MC324 Pin ##

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5053

Internal Error 5053: EP_fixup(): invalid polarity type

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5054

Logical Error 5054: Polarity of 'xxx.OE' pin ## does not match with that of the enable

Invert the OE equation.


Internal Error 5055

Internal Error 5055: E0600_fixup(): OE has to be a select mux

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5056

Internal Error 5056: E1800_fixup OE has to be a select mux

Contact the Xilinx Support Website at www.xilinx.com.


Warning 5057

Warning 5057: Only the first ## signature chars will be programmed

Use only one word with -ues signature_word.


Internal Error 5058

Internal Error 5058: Too many product terms on pin ###

Contact the Xilinx Support Website at www.xilinx.com.


Fatal Error 5059

Fatal Error 5059: Too many terms used. ## max; try group reduction

Read the Design Considerations chapter in the ABEL-HDL Reference on Polarity Control.


Internal Error 5060

Internal Error 5060: Too many bits in PROM word

Contact the Xilinx Support Website at www.xilinx.com.


Command Error 5061

Command Error 5061: Invalid output type for PROM ##

Use -format with one of the valid type for PROM.


Warning 5062

Warning 5062: Input/feedback xxxxxx has been reduced out

The Reduce Logic process has reduced out the input.


Logical Error 5063

Logical Error 5063: Input xxx has no 'uncomplemented' array connection

Invert the input.


Logical Error 5064

Logical Error 5064: Input xxx has no 'complement' array connection

Invert the input.


Logical Error 5065

Logical Error 5065: Local feedback xxxxxx can't be used in quadrant ##

Use feedback that can feed to any quadrant (global feedback).


Internal Error 5066

Internal Error 5066: Startfuse #### is not start of term

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5067

Internal Error 5067: Startfuse #### is not in any array

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5068

Internal Error 5068: fuseinc of array nn is zero

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5069

Logical Error 5069: Select mux xxx can't be re-configured

Check the equation for conflicting setting of the macrocell.


Logical Error 5070

Logical Error 5070: xxx requires pin ## as its input

Modify the equation to use the pin as input.


Logical Error 5071

Logical Error 5071: Pin ## can't be assigned to xxx

Reassign pin for the equation with a valid output pin.


Internal Error 5072

Internal Error 5072: rpt_resrc(): Illegal feedback

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5073

Logical Error 5073: ? not an odd # of pins on side of device for PLCC.

Strange PLCC; ignore the message.


Warning 5074

Warning 5074: Signal xxx was declared but not used

Make sure this is not a mistake.


Internal Error 5076

Internal Error 5076: Get_reg_str bad reg type

Contact the Xilinx Support Website at www.xilinx.com.


Fatal Error 5078

Fatal Error 5078: Writing to document file xxx

Run cleanup4 to make room in the directory.


Internal Error 5079

nternal Error 5079: Missing keyword %s in xxx.fus

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5080

Internal Error 5080: ## fuses in a set; exceed ## limit in xxx.fus

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5081

Internal Error 5081: 'c' expected, 'c' found while reading xxx.fus

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5082

Logical Error 5082: Fuse #### in xxx.fus is out of range

Check the fuses statement for invalid fuse numbers.


Fatal Error 5083

Fatal Error 5083: EOF found when writing X to JEDEC Hex file

Run cleanup4 to make room in the directory.


Fatal Error 5084

Fatal Error 5084: EOF found when writing X to JEDEC file

Run cleanup4 to make room in the directory.


Internal Error 5085

Internal Error 5085: negative jedec number

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5086

Internal Error 5086: No symbol found in xxx.tmv

Contact the Xilinx Support Website at www.xilinx.com.


Warning 5087

Warning 5087: Only one feedback is allowed on pin ##; mapping xxx to xxx.FB

Check the feedback for incorrect use by the software.


Command Error 5088

Command Error 5088: Programmer load file not specified. Use -o filename

Run fuseasm infile -o filename.jed


Fatal Error 5089

Fatal Error 5089: Format code ## is not allowed. Use -format default

Run fuseasm infile -format default.


Internal Error 5090

Internal Error 5090: Illegal character xx found while reading xxx.tmv

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5091

Internal Error 5091: xx expected. xx found while reading xxx.tmv

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5092

Logical Error 5092: xxx node ## can't use shared feedback

Move one of the two equations that use shared feedback to another free pin.


Logical Error 5095

Logical Error 5095: PR/RE is not allowed for latched output xxx

Remove PR/RE equation for latched output.


Internal Error 5096

Internal Error 5096: Cluster has been clobbered

Contact the Xilinx Support Website at www.xilinx.com.


Fatal Error 5097

Fatal Error 5097: Pin ## is an illegal pin assignment for xxx

Pin is out of range, try some other device.


Fatal Error 5098

Fatal Error 5098: Equation file type is not supported

Run plaopt infile -reduce default.


Internal Error 5099

Internal Error 5099: Invalid output pin ##

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5100

Internal Error 5100: Pal_choose bad pin ## index

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5101

Internal Error 5101: get_node(): illegal extension

Contact the Xilinx Support Website at www.xilinx.com.


Warning 5102

Warning 5102: Polarity of yyy is not specified. Assume pos polarity

Output has programmable inversion both before and after register.


Warning 5103

Warning 5103: Polarity of yyy is not specified. Pin has neg polarity

Output has fixed inversion after register; it may invert the PR/RE output.


Internal Error 5104

Internal Error 5104: oe_choose(): bad enable type

Contact the Xilinx Support Website at www.xilinx.com.


Internal Error 5105

Internal Error 5105: comb_choose pSIG ## is null

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5106

Logical Error 5106: xxx can't map to node ##; wrong polarity

Output has fixed polarity type which is different from the equation; run Reduce Logic with the Reduction Algorithm property default.


Logical Error 5107

Logical Error 5107: xxx can't map to pin ##; wrong polarity

Output has fixed polarity type which is different from the equation; run Reduce Logic with the Reduction Algorithm property default.


Internal Error 5108

Internal Error 5108: invalid_output_pin(): bad pinty for pin ##

Contact the Xilinx Support Website at www.xilinx.com.


Logical Error 5109

Logical Error 5109: xxx istype 'BUFFER' is not allowed on pin ##

Select a device with no (or programmable) inversions.


Logical Error 5110

Logical Error 5110: xxx istype 'INVERT' is not allowed on pin ##

Select a device with fixed or programmable inversions.


Logical Error 5111

Logical Error 5111: PR/RE is not allowed for combinational output xxx

Modify to the primary equation to be registered.


Logical Error 5112

Logical Error 5112: xxx.XR can't be used with xxx.T

XOR is required to perform D-T emulation.


Command Error 5113

Command Error 5113: No input file specified

Run fuseasm with a valid Equation file.


Logical Error 5114

Logical Error 5114: Input to register xxx can only be from pin ##

Check the equation for improper input register assignment.


Command Error 5115

Command Error 5115: Illegal use of options

Check the command line options for illegal flags.


Fatal Error 5116

Fatal Error 5116: Device not supported by FUSEASM

The device is not supported by the specified program.


Warning 5117

Warning 5117: Test vector has conflicting input and output values for pin ##

The signal on the named pin was specified on both the input and output side of the test vectors, but with conflicting values.


Logical Error 5118

Logical Error 5118: ## too many universal terms used for output xxx pin ##

This device has both universal and regional product terms. The specified signal has more universal input signals than there are available universal product terms.


Logical Error 5119

Logical Error 5119: ## too many regional terms used for output xxx pin ##

This device has both universal and regional product terms. The specified signal has more regional input signals than there are available regional product terms.


Logical Error 5120

Logical Error 5120: xxx can't be used as input to yyy; quadrants differ

The two named signals are in different quadrants of a multi-array device, and cannot be connected.


Logical Error 5121

Logical Error 5121: xxx ##'s PT can't be steered to yyy ##

A problem has occurred in the product term allocation. Contact Customer Support.


Fatal Error 5122

Fatal Error 5122: xxx device not supported by 'yyyy'

The named device is not supported by the specified program. This usually indicates a problem with the device file. Contact Customer Support.


Logical Error 5123

Logical Error 5123: Adjacent feedback conflict on pin ##. Two signals need the same feedback path

This device allows a macrocell to use it's neighbor's feedback path. Because of the signal placement, a conflict has been created where two signals require the same feedback path.


Logical Error 5124

Logical Error 5124: Cannot use clock pin 1 as both Input and Register Clock

The specified pin cannot be used as BOTH an input and a clock pin. The functions are mutually exclusive.


Fatal Error 5126

Fatal Error 5126: Invalid switch matrix input: Block ##, PLB ##, IN ##

A problem has occurred in the switch-matrix routing. Contact Customer Support.


Fatal Error 5127

Fatal Error 5127: Device file error: pin ## is incorrect parent pin of node ##

Indicates a problem with the device file. Contact Customer Support.


Fatal Error 5128

Fatal Error 5128: ## to ## is invalid steering: invalid pin/node

A problem has occurred in the product term allocation. Contact Customer Support.


Fatal Error 5129

Fatal Error 5129: ## to ## is invalid steering: pin/node has no product terms

A problem has occurred in the product term allocation. Contact Customer Support.


Fatal Error 5130

Fatal Error 5130: ## to ## is invalid steering: ## steered more than once

A problem has occurred in the product term allocation. Contact Customer Support.


Logical Error 5131

Logical Error 5131: Equation at pin ##; Register.Q feedback with combinatorial output

Registered feedback was specified from a combinational equation. Remove the .Q extension from the combinational signal.


Warning 5132

Warning 5132: swapping RESET and PRESET terms of signal ##

Fuseasm is swapping the reset and preset equations on the output register for signal.


Logical Error 5133

Logical Error 5133: Hardwired enable: ## pin ## can't be used as pterm input to signal ##

Enable signal cannot be wired to product term array. Remove enable signal from input equation.


Logical Error 5134

Logical Error 5134: Hardwired clock signal: ## pin ##, cannot be used as input to signal ##

Clock signal cannot be wired to product term array. Remove clock signal from input equation.


Logical Error 5135

Logical Error 5135: signal ## requires regional product term equation

Signal must be not be wired with universal product term equation. Wire signal with regional product term equation.


Logical Error 5136

Logical Error 5136: ##.PIN feedback not available with register output

Design must use register feedback (.Q or .FB) when register output is specified.


Internal Error 5137

Internal Error 5137: Invalid keyword: ### in fitter fmp file

The *.fmp file produced by the fitter contains an unsupported KEYWORD format.


Internal Error 5138

Internal Error 5138: Bad MACRO table symbolic assignment for node ###

The *.fmp file produced by the fitter contains an unsupported MACRO table assignment. The pin/node can not have a symbolic assignment.


Fatal Error 5139

Fatal Error 5139: Illegal node selection for CSM: ###

The *.fmp file produced by the fitter contains an unsupported Central Switch Matrix routing assignment.


Fatal Error 5140

Fatal Error 5140: Can't program default for Block ###, PLB ###

The *.fmp file produced by the fitter contains an unsupported Central Switch Matrix routing assignment.


Logical Error 5141

Logical Error 5141: Two signals need the same feedback path

One too many feedback paths specified. Register feedback must be used locally, and cannot be used by the adjacent macrocell.


Internal Error 5142

nternal Error 5142: Invalid MACRO table format in fitter fmp file

The *.fmp file produced by the fitter contains unsupported MACRO table keyword assignment. MACRO section keyword must be followed by total number of node assignments.


Internal Error 5143

Internal Error 5143: Invalid format in fmp file

The *.fmp file produced by the fitter contains unsupported MACRO table format. The *.fmp file may be empty.


Fatal Error 6002

Fatal Error 6002: Error writing to output

The disk does not have enough free space to contain the file being written.


Fatal Error 6006

Fatal Error 6006: Device type must be specified

The device type must be specified on the command line if the JEDEC file does not have the device type in the header. The JEDEC file header could be modified to include the following text string: "JEDEC file for: P16R8".


Fatal Error 6007

Fatal Error 6007: Could not open vector file xxx

The ".tmv" vector file produced by the compiler could not be opened, or there were no test vectors in the ABEL-HDL source file. If the .tmv file was deleted, reprocess the ABEL-HDL source file.


Fatal Error 6029

Fatal Error 6029: Single number expected in '-signal' xxx

Note A valid decimal number was not found in the Signal property. (range values (14..17) are not supported.)


Fatal Error 6030

Fatal Error 6030: No breakpoint vector number(s) found

A valid decimal number was not found in the breakpoint property field.


Fatal Error 6031

Fatal Error 6031: No signals found in '-signal' list

No signal names or numbers were found in the Signal property.


Warning 6032

Warning 6032: '-signal' signal xxx not found in device

The indicated signal was not found in the device. If the signal is hierarchical, refer to the Cross Reference report to determine the appropriate short name to use. (signal names are case sensitive.)


Warning 6033

Warning 6033: No matching signals found in '-signal' list, using defaults

No matching signals were found. If the desired signals are hierarchical, refer to the Cross Reference report to determine the appropriate short names to use. (signal names are case sensitive.)


Fatal Error 6034

Fatal Error 6034: File name too long xxx

The indicated file name is too long.


Fatal Error 6035

Fatal Error 6035: Reading input part of test vector

The .tmv test vector file is defective. Reprocess the ABEL-HDL source to regenerate the .tmv file. If this error persists contact the Customer Resource Center.


Fatal Error 6036

Fatal Error 6036: Reading test vector '-'

The .tmv test vector file is defective. Reprocess the ABEL-HDL source to regenerate the .tmv file. If this error persists contact the Customer Resource Center.


Fatal Error 6037

Fatal Error 6037: Reading output part of test vector

The .tmv test vector file is defective. Reprocess the ABEL-HDL source to regenerate the .tmv file. If this error persists contact the Customer Resource Center.


Fatal Error 6038

Fatal Error 6038: Reading test vector ';'

The .tmv test vector file is defective. Reprocess the ABEL-HDL source to regenerate the .tmv file. If this error persists contact the Customer Resource Center.


Warning 6040

Warning 6040: Pin # must be high for proper flip-flop operation

Found during synchronous output operation calculation.


Warning 6041

Warning 6041: Pin # must be high for proper flip-flop operation

Found during asynchronous output operation calculation.


Fatal Error 6051

Fatal Error 6051: Multiple .C, .LE or .LH specified for xxx

Only one clock input is allowed for a register. Remove the unnecessary equation and reprocess the design.


Warning 6052

Warning 6052: Second part of xxx XOR equation not found in the equation file filename

Two parts of an XOR equation must be present, indicated with a .X1 and .X2 suffix. The equation file was missing one half of the XOR equation.


Warning 6054

Warning 6054: No clock equation found for xxx

The Equation Simulator requires a clock equation for each registered equation.


Fatal Error 6055

Fatal Error 6055: Incomplete design, can not simulate

Information required by the Equation Simulator was missing from the Equation file.


Fatal Error 6056

Fatal Error 6056: Input file not specified

A Equation file is expected as the input to the Equation Simulator.


Fatal Error 6057

Fatal Error 6057: Could not open input file xxx

Check to make sure the input file exists and that you have read/write access.


Fatal Error 6058

Fatal Error 6058: Default output name requires input file with a .TTn extension

To use the default output filename, the input file must have a .tt# extension.


Fatal Error 6059

Fatal Error 6059: Could not open output file xxx

The disk does not have enough free space to contain the file being written.


Fatal Error 6060

Fatal Error 6060: Vector file not specified

A ".tmv" test vector file must be specified on the command line with the "-ivector" option or in the Equation file with a "VECTORFILE" comment.


Fatal Error 6061

Fatal Error 6061: Could not open vector file xxx

The ".tmv" vector file produced by the compiler could not be opened by Equation Simulator. If it was deleted, rerun the compiler to recreate it.


Fatal Error 6062

Fatal Error 6062: Could not open input file xxx

The ".tt0" Equation file produced by BLIFOPT could not be opened by Equation Simulator. If the file was deleted, reprocess the design to recreate it.


Fatal Error 6063

Fatal Error 6063: Could not open output file xxx

The indicated working file could not be opened by Equation Simulator.


Fatal Error 6064

Fatal Error 6064: Could not open input file xxx

The indicated working file could not be opened by Equation Simulator.


Fatal Error 6065

Fatal Error 6065: Equation file has ## signals, the limit is ##

The number of input and output signals in the Equation file exceed the maximum allowed in Equation Simulator.


Internal Error 6066

Internal Error 6066: Unknown extension xxx on PLA output

The Equation file is defective.


Fatal Error 6070

Fatal Error 6070: Conflicting signals 'xxxx' and 'xxxx'

Cannot specify more than one output equation for an output pin or node.


Warning 6071

Warning 6071: Multiple register feedback specified for 'xxxx'

Cannot specify multiple feedback equations (for example, xxx.Q and xxx.FB) from state register.


Warning 6073

Warning 6073: Initial state 'xxxx' not found

The initial state was not one of the defined state names.


Warning 6074

Warning 6074: 'xxxx' does not have a primary equation

Design must specify a primary equation for signal 'xxxx'.


Warning 6100

Warning 6100: Skipping unknown JEDEC field xx

A reserved field identifier was used. Check the JEDEC file.


Fatal Error 6101

Fatal Error 6101: L field address exceeds fuse limit ##

The fuses specified in the L field exceeded the maximum allowable fuse address for the device. This error could be caused by selecting the wrong device.


Fatal Error 6102

Fatal Error 6102: Fuse address ## exceeds fuse limit ##

While processing a string of fuses in a L field, the calculated fuse address exceeded the maximum allowable fuses address for the device. This error could be caused by selecting the wrong device.


Fatal Error 6103

Fatal Error 6103: Illegal fuse state xx at fuse address ##

The allowable fuse states for a L field are "1" and "0".


Fatal Error 6104

Fatal Error 6104: H field address exceeds fuse limit ##

The fuses specified in the H field exceeded the maximum allowable fuses address for the device. This error could be caused by selecting the wrong device.


Fatal Error 6105

Fatal Error 6105: Fuse address ## exceeds fuse limit ##

While processing a string of fuses in a H field, the calculated fuse address exceeded the maximum allowable fuses address for the device. This error could be caused by selecting the wrong device.


Fatal Error 6106

Fatal Error 6106: Illegal fuse state xx at fuse address ##

The allowable fuse states for a H field are "0" through "9" and "A" through "F".


Fatal Error 6107

Fatal Error 6107: Illegal default fuse state xx

The allowable default fuse states are "0" and "1".


Warning 6108

Warning 6108: Illegal default test condition xx

The allowable default test conditions are "0" and "1".


Fatal Error 6109

Fatal Error 6109: QF value ## incorrect, ## fuses expected

The number of fuses specified in the JEDEC QF field doesn't agree with the device file.


Fatal Error 6110

Fatal Error 6110: QP value ## incorrect, '##' pins expected

The number of pins specified in the JEDEC QP field doesn't agree with the device file.


Fatal Error 6111

Fatal Error 6111: QV value ## is to large, '##' vectors allowed

JEDEC Simulator is limited to 65000 bytes of memory for test vector storage. This means a 24 pin device can have a maximum of 2708 vectors and a 68 pin device can have up to 955 vectors.


Warning 6112

Warning 6112: File Fuse Checksum = #### RAM Fuse Checksum = ####

The calculated fuse checksum didn't match the value in the C field.


Warning 6114

Warning 6114: Hex number expected

Allowed hexadecimal digits are "0" through "1" and "A" through "F".


Warning 6115

Warning 6115: Hex number too large

Hexadecimal number was to large, normal limit is 4 digits.


Fatal Error 6116

Fatal Error 6116: Expecting end of field character '*'

The field had extra characters.


Warning 6117

Warning 6117: Vector ## is out of sequence

A test vector was missing or out of sequence.


Warning 6118

Warning 6118: Wrong number of test conditions in vector ##

The test vectors should have the same number of test conditions as the QP field.


Warning 6119

Warning 6119: PIN or NODE xxx has invalid or missing number

The PIN and NODE note fields require a number for each signal.


Warning 6120

Warning 6120: Pin or node ## has multiple names xxx and yyy

The PIN and NODE note fields require a unique number for each signal.


Internal Error 6130

Internal Error 6130: Feedback on pins ## and ## have the same array offset

This usually indicates a problem with the device file. Contact Customer Support.


Internal Error 6131

Internal Error 6131: Invalid array offset ##

This usually indicates a problem with the device file. Contact Customer Support.


Internal Error 6132

Internal Error 6132: 64KB memory segment limit, use DOS-Extender version

The Design is too large for the non DOS-Extended version of the simulator.


Fatal Error 6133

Fatal Error 6133: Could not open status file xxx.sts

Check to make sure that the output file xxx.sts is accessible.


Fatal Error 6135

Fatal Error 6135: Empty Logic file! Equation Simulator can't simulate

Equation Simulator expected logic in the Equation file (.ttn). The .ttn file might be corrupted, empty, or contain only headers. Manually add logic to your .ttn file or create a new .ttn file by compiling your design using Compile Logic. When your .ttn contains logic, resimulate your design using Equation Simulator.


Fatal Error 6136

Fatal Error 6136: No Clock assignment for signal 'xxx'

Missing signal 'xxx.C' assignment in the design source file. This message appears if one of the following conditions occurs:

  • The signal is declared as a register but no clock is assigned to it.

  • The signal is declared as a combinational signal and used with the .Q feedback extension but no clock is assigned to it.

To solve this problem, try adding an assignment for the signal 'xxx.C' to your design.


Warning 6137

Warning 6137: Power-up value was not given, set to default value: 0

The option -initial is used but no value is given following the flag.


Warning 6138

Warning 6138: Signal 'xxx' can't be found for test vectors simulation

The signal 'xxx' is listed in the test vectors (i.e. in .TMV or .ABV file) but there is no equation associates with that signal. Please look at the design and check whether the signal has been declared and used. See also, Error Message 5074.


Fatal Error 6500

Fatal Error 6500: Input file not specified

No input JEDEC file was specified on the command line.


Fatal Error 6501

Fatal Error 6501: Could not open input file 'xxxx'

The indicated file could not be opened by JED2AHDL. If the file exists, check to make sure that it has the appropriate file protection settings to enable you to access it.


Fatal Error 6502

Fatal Error 6502: Could not open output file 'xxxx'

The indicated file could not be opened for write. Check that you have available disk space, the specified path is valid, and the file directory protection allows you write access.


Fatal Error 6503

Fatal Error 6503: Device type must be specified

There is no device name specified in the JEDEC file. You must specify a device name on the command line in this case.


Fatal Error 6504

Fatal Error 6504: Could not open report file 'xxxx'

The indicated file could not be opened for write. Check that you have available disk space, the specified path is valid, and the file directory protection allows you write access.


Logical Error 6505

Logical Error 6505: PROMs are not supported by JED2AHDL

JED2AHDL cannot translate PROM devices.


Logical Error 6506

Logical Error 6506: Device not supported by JED2AHDL

This device cannot be translated by JED2AHDL. This usually means that the device contains some complex feature that is not supported in the JED2AHDL translator.


Internal Error 6507

An internal program error has occurred. Contact the Xilinx Support Website at www.xilinx.com.


Fatal Error 6508

Fatal Error 6508: Error writing to disk

Check that disk space is available, and that the directory is not write protected.


Logical Error 6509

Logical Error 6509: unknown f/f type 'nn' on pin 'nn'

A flip-flop type was encountered that is not known to JED2AHDL. Contact the Xilinx Support Website at www.xilinx.com.


Fatal Error 6510

Fatal Error 6510: Could not rename 'xxxx' to 'yyyy'

If an ABEL source file exists that has the same name as the source file that JED2AHDL will create, it renames the existing file to "name.bak". This error indicates the rename failed. This is usually indicative of a file protection problem.


MUXADD Source File

module MuxAdd

title '5-bit ripple adder with input multiplex'

muxadd device 'P22V10';

AddClk,Clr,Add10,Sub10,is_Ace pin 1,9,8,7,14;

V4..V0 pin 6..2;

S4..S0 pin 15..19;

C4..C1 pin 20..23;

X,C,L,H = .X., .C., 0, 1;

Card = [V4..V0];

Score = [S4..S0];

CarryIn = [C4,,C1, 0];

CarryOut = [X, C4..C1];

ten = [0, 1, 0, 1, 0];

minus_ten = [1, 0, 1, 1, 0];

S4..S0 istype 'reg'';

''input multiplexer

Data = Add10 & Sub10 & Card

# !Add10 & Sub10 & ten

# Add10 & !Sub10 & minus_ten;

equations

Score := Data $ Score.fb $ CarryIn;

CarryOut = Data & Score.fb # (Data # Score.fb) & CarryIn;

Score.ar = !(Clr # Clr);

Score.clk = AddClk;

is_Ace = Card == 1;

''test_vectors edited...

end MuxAdd


Node Keyword

Syntax

[!]node_id[,[!]node_id...] NODE [node#s...] [ISTYPE 'attr'];

node_id - An identifier used for reference to a node in a logic design.

node #s - The node number on the real device.

attr - A string that specifies node attributes for devices with programmable nodes.

Use

The NODE keyword is used to declare those signals that may be assigned to buried nodes within a device.

Example

The node attribute string, Istype 'attr', specifies node attributes. The node declaration,

B NODE istype 'reg' ;

specifies that node B is a buried flip-flop.

a0..a3 node 22..25;

Assigns a0, a1, a2, and a3 to nodes 22, 23, 24, and 25, respectively.


Operator Priority

The table below summarizes the logical, arithmetic and relational operators, presented in groups according to their priority. Priority 1 is the highest priority (performed first), and priority 4 is the lowest (performed last). With two operators of the same priority, the operations are performed left to right.

Priority | Operator | Description
1 | - | negate
1 | ! | NOT
2 | & | AND
2 | << | shift left
2 | >> | shift right
2 | * | multiply
2 | / | unsigned division
2 | % | modulus
3 | + | add
3 | - | subtract
3 | # | OR
3 | $ | XOR: exclusive OR
3 | !$ | XNOR: exclusive NOR
4 | == | equal
4 | != | not equal
4 | < | less than
4 | <= | less than or equal
4 | > | greater than
4 | >= | greater than or equal

When you have operators of the same priority in the same expression, the operations are performed from left to right. You can use parentheses to change the order of evaluation, with the operation in the innermost set of parentheses performed first. Some examples of expressions are given below. Note how the order of operations and the use of parentheses affect the evaluated result.

Expression | Result | Description
2 * 3/2 | 3 | operators with same priority
2 * 3 / 2 | 3 | spaces are insignificant
2 * (3/2) | 2 | fraction is truncated
2 + 3 * 4 | 14 | multiply first
(2 + 3) * 4 | 20 | add first
2#4$2 | 4 |
2#(4$2) | 6 |
2 == ^hA | 0 | false
14 == ^hE | -1 | true


Operators

ABEL-HDL operators are divided into four basic types: logical, arithmetic, relational, and assignment. The table below shows all of the operators, and each type is discussed in a separate topic.

Logical | Arithmetic | Relational | Assignment | Range
! | - | == | = | ..
& | + | != | := |
# | * | < | ?= |
$ | / | <= | ?:= |
!$ | % | > |  |
<< | >= |  |  |
>> |  |  |  |


Pin Keyword

Syntax

[!]pin_id[,[!]pin_id...] PIN [pin#[,pin#]] [ISTYPE 'attr'];

pin_id - An identifier used to refer to a pin throughout a module.

pin# - The pin number on the real device.

attr - A string that specifies pin attributes for devices with programmable pins.

Use

The PIN keyword is used to declare those input and output signals that must eventually be available on a device I/O pin. You should also specify pin attributes for all pins used as outputs.

When lists of pin_ids and pin #s are used in one pin declaration statement, there is a one-to-one correspondence between the identifiers and numbers given. If you declare pin numbers, you must include numbers for each identifier listed in the statement.

Example

!Clock, Reset, S1 PIN 12,15,3;

This pin declaration assigns the pin name, Clock to pin 12; Reset to pin 15; and S1 to pin 3.

The use of the "!' operator in pin declarations indicates that the pin is active-low and will be automatically negated when processed by the language processor.

Errors

The following are pin assignment errors that cause errors in ABEL:

Assigning the same pin number to two signals (A1, A0 pin 17,17;).

Assigning invalid pin numbers when a device has been specified (Q3 pin 28 in a 20 pin device). The fitter for a device can optionally correct invalid pin assignments.


Pin-to-pin vs. Detailed Descriptions for Registered Designs

ABEL-HDL assignment operators can be used when writing high-level equations. The = operator specifies a combinational assignment, where the design is written with only the circuit's inputs and outputs in mind. The := operator specifies a registered assignment, where you must consider the internal circuit elements (such as output inverters, presets and resets) related to the memory elements (typically flip-flops). The semantics of these two assignment operators is discussed below.

Using := for Pin-to-pin Descriptions

The := implies a memory element is associated with the output defined by the equation. For example, the equation

Q1 := !Q1 # Preset;

implies that Q1 will hold its current value until the memory element associated with that signal is clocked (or unlatched, depending on the register type).

This equation is a pin-to-pin description of the output signal Q1. The equation describes the signal's behavior in terms of desired output pin values for various input conditions. Pin-to-pin descriptions are useful when describing a circuit that is completely architecture-independent.

Language elements that are useful for pin-to-pin descriptions are the := operator, and the .CLK, .OE, .FB, .CLR, .ACLR, .SET, .ASET and .COM dot extensions. These dot extensions help to resolve circuit ambiguities when describing architecture-independent circuits.

Pin-to-pin Descriptions

A pin-to-pin description of a device-based circuit is a description that refers only to the relationship between the device's input pins and corresponding values observed on the output pins. Pin-to-pin descriptions do not include information about macrocell configurations, flip-flop types, or the precise form of the logic programmed into the device.

The pin-to-pin example contains a complete pin-to-pin specification of a simple 2-bit counter with a reset.

Detailed Descriptions

Pin-to-pin designs are easier to move to alternative device types, and are easier to comprehend. However, detailed designs using ABEL dot extensions are often required to describe complex or device-specific features in a circuit. These device features are usually associated with flip-flops and cannot be described using pin-to-pin design descriptions.

The detailed example contains the same design as the example above, except using detailed methods to take advantage of devices that have a built-in register reset.

Mixed Descriptions

You can mix pin-to-pin and detailed description methods in the same design. The mixed example contains a source file where only the reset function is described using detailed design methods; the rest of the circuit is described pin-to-pin.


Pin-to-Pin Dot Extensions

Pin-to-Pin Dot Extensions for CPLD Designs

Dot Extension | Function Description | Supported in Hardware | Emulated | Not Supported
.ACLR | Asynchronous Reset | X |  |
.ASET | Asynchronous Preset | X |  |
.CLR | Synchronous Reset |  | X |
.COM | Combinational Feedback from Flip-Flop Data Input, Normalized to the Pin Value |  |  | X
.FB | Register Feedback | X |  |
.SET | Synchronous Preset |  | X |


Property Keyword

Syntax

xilinx PROPERTY 'string' ;

Use

The PROPERTY declaration statement allows you to specify additional design information associated with the Xilinx core tools.

The "xilinx" property_id is used to identify properties relevant to the Xilinx core tools, and the string argument contains the actual property data.


ABEL Syntax Reference

ABEL-HDL Language Syntax Reference

This reference contains detailed information about each of the language elements in ABEL-HDL; it assumes you are familiar with basic ABEL-HDL syntax .

.ext - Dot Extensions

= - Constant Declarations

@Directives

Intermediate Expressions

ABEL-HDL Keywords

Async_reset | Interface (submodule) | State_register
Bus | Istype | Sync_reset
Case | Library | Test_Vectors
Declarations | Macro | Title
Device | Module | Trace
End | Node | Truth_Table Keyword
Equations | Pin | When-Then-Else
Functional_block | Property | With
Fuses | State (Declaration) | XOR_Factors
Goto | State (In State_Diagram) |
If-Then-Else | State_Diagram |
Interface (top module) |  |


Relational Operators

Operator | Result | Description
== | Equal | Double equal sign
!= | Not equal | exclamation point/equal sign
< | Less than | left angle bracket
<= | Less than or equal | left angle bracket/equal sign
> | Greater than | right angle bracket
>= | Greater than or equal | right angle bracket/equal sign

Relational operators are used to compare two items in an expression. Expressions formed with relational operators produce a Boolean true or false value.

All relational operations are unsigned. For example, the expression !0 > 4 is true since the complement of !0 is 1111 (assuming 4 bits of data), which is 15 in unsigned binary, and 15 is greater than 4. For the purpose of this example, a four-bit representation was assumed; in actual use, !0, the complement of 0, is 32 bits all set to 1.

Examples

Expression | Value
2 == 3 | False
2 != 3 | True
3 < 5 | True
-1 > 2 | True

The logical values, true and false, are represented internally by numbers. Logical true is -1 in twos complement: all 32 bits are set to 1. Logical false is 0 in twos complement so all 32 bits are set to 0. This means that an expression producing a true or false value (a relational expression) can be used anywhere a number or numeric expression could be used and -1 or 0 will be substituted in the expression depending on the logical result.

For example, A = D $ (B == C); means that

A equals the complement of D if B equals C

A equals D if B does not equal C.

When using relational operators, always use parentheses to ensure the expression is evaluated in the order you expect. The logical operators & and # have a higher priority than the relational operators. The following equation

Select = [A15..A0] == ^hD000 # [A15..A0] ==<N>^h1000;

has the default parentheses grouping

Select = [A15..A0] == (^hD000 # [A15..A0]) ==<N>^h1000;

which is not the intended equation. To get the desired results, write the equation as follows:

Select = ([A15..A0] == ^hD000) # ([A15..A0] ==<N>^h1000);


Sample Source File

Module sample
Title 'Sample Source File'
Declarations
I1..I3, Clk Pin 11..13, 1 ; " range operator used for I1, I2, I3
S1..S3 Pin 24,25,34 Istype 'reg_d' ;
C = .C. ; "constant .C. mapped to C identifier
Set1 = [S1..S3] ;
Set2 = [I3,I1,I2];
Equations
Set1.clk = Clk ;
Set1 = Set2;
Test Vectors ([Clk,Set1]->[Set2])
[ C , 3 ]->[ 3 ];
End sample


Source File - BINBCD

module BINBCD

title 'comparator and binary to BCD decoder for blackjack machine'

''The 5-bit binary score (0-31) is converted into two BCD outputs.

''The integer division '/' and the modulus operator '%' are used

''to extract the individual digits from the two digit score.

'''Score % 10' will yield the 'units' and

'''Score / 10' will yield the 'tens'.

''

''The 'GT16' and 'LT22' outputs are for the state machine controller.

binbcd device 1P16L8';

S4..S0 pin 5..1;

score = [S4..S0];

LT22,GT16 pin 12,13 istype 'com';

D5,D4 pin 14,15 istype 'com';

bcd2 = [D5,D4];

D3..D0 pin 16..19 istype 'com';

bcd1 = [D3..D0];

''digit separation macros

binary = 0; ''scratch variable

clear macro (a) {@const ?a=0};

inc macro (a) {@const ?a=?a+1;};

equations

LT22 = (score < 22); ''Bust

GT16 = (score > 16); ''Hit / Stand

''test_vectors edited...

truth_table ( score -> [bcd2,bcd1])

0 -> [ 0 , 0 ];

1 -> [ 0 , 1 ];

2 -> [ 0 , 2 ];

3 -> [ 0 , 3 ];

4 -> [ 0 , 4 ];

5 -> [ 0 , 5 ];

6 -> [ 0 , 6 ];

7 -> [ 0 , 7 ];

8 -> [ 0 , 8 ];

9 -> [ 0 , 9 ];

10 -> [ 1 , 0 ];

11 -> [ 1 , 1 ];

12 -> [ 1 , 2 ];

13 -> [ 1 , 3 ];

14 -> [ 1 , 4 ];

15 -> [ 1 , 5 ];

16 -> [ 1 , 6 ];

17 -> [ 1 , 7 ];

18 -> [ 1 , 8 ];

19 -> [ 1 , 9 ];

20 -> [ 2 , 0 ];

21 -> [ 2 , 1 ];

22 -> [ 2 , 2 ];

23 -> [ 2 , 3 ];

24 -> [ 2 , 4 ];

25 -> [ 2 , 5 ];

26 -> [ 2 , 6 ];

27 -> [ 2 , 7 ];

28 -> [ 2 , 8 ];

29 -> [ 2 , 9 ];

30 -> [ 3 , 0 ];

31 -> [ 3 , 1 ];

''This table could be replaced with the following macro:

'' clear(binary);

'' @repeat 32 {

'' binary -> [binary/10,binary%10]; inc(binary);}

''

''the test vectors demonstrate the use of the macro

test_vectors ( score -> [bcd2,bcd1])

clear (binary);

@repeat 32 {

binary -> [binary/10,binary%10]; inc(binary);}

end


Source File - BJACK

module bjack

title 'Blackjack state machine controller'

bjack device 'P16R6

''Inputs

Clk,ClkIn pin 1,1; ''system clock

GT16,LT22 pin 3,4; ''score less than 17 and 22

is_Ace pin 5; ''card is ace

Restart pin 6; ''restart game

CardIn,CardOut pin 7,8; ''card present switches

Ena pin 11;

Sensor = [CardIn,CardOut];

_In = [ 0 , 1 ];

InOut = [ 1 , 1 ];

Out = [ 1 , 0 ];

''Outputs

AddClk pin 12 istype 'com'; ''Adder clock

Add10 pin 13 istype 'reg_D,invert'; ''Input Mux control

Sub10 pin 13 istype 'reg_D,invert'; ''Input Mux control

Q2,Q1,Q0 pin 15,16,17 istype 'reg_D,invert';

Ace pin 18 istype 'reg_D,invert'; ''Ace memory

High,Low = 1,0;

H,L,C,X = 1,0,.C.,.X.; ''test vector characters

Qstate = [Add10,Sub10,Q2,Q1,Q0];

Clear = [ 1 , 1 , 1, 1, 1]; ''31

ShowHit = [ 1 , 1 , 1, 1, 0]; ''30

AddCard = [ 1 , 1 , 0, 0, 0]; ''24

Add_10 = [ 0 , 1 , 0, 0, 0]; ''16

Wait = [ 1 , 1 , 0, 0, 1]; ''25

Test_17 = [ 1 , 1 , 0, 1, 0]; ''26

Test_22 = [ 1 , 1 , 0, 1, 1]; ''27

ShowStand = [ 1 , 1 , 1, 0, 0]; ''28

ShowBust = [ 1 , 1 , 1, 0, 1]; ''29

Sub_10 = [ 1 , 0 , 0, 0, 1]; ''17

Zero = [ 0 , 0 , 0, 0, 0]; ''0

equations

[Qstate,Ace].c = Clk;

[Qstate,Ace].oe = !Ena;

@dcset

state_diagram Qstate

State Clear: AddClk = !ClkIn;

Ace := Low;

if (Restart == Low) then Clear else ShowHit;

State ShowHit: AddClk = Low;

Ace := Ace;

if (CardIn == Low) then AddCard else ShowHit;

State AddCard: AddClk = !ClkIn;

Ace := Ace;

If (is_Ace & !Ace) then add_10 else Wait;

State Add_10: AddClk = !ClkIn;

Ace := High;

goto Wait;

State Wait: AddClk = Low;

Ace := Ace;

if (CardOut == Low) then Test_17 else Wait;

State Test_17: AddClk = Low;

Ace := Ace;

if !GT16 then ShowHit else Test_22;

State Test_22: AddClk = Low;

Ace := Ace;

case LT22 : ShowStand;

!LT22 & !Ace : ShowBust;

!LT22 & Ace : Sub_10;

endcase;

State Sub_10: AddClk = !ClkIn;

Ace := Low;

goto Test_17;

State ShowBust: AddClk = Low;

Ace := Ace;

if (Restart == Low) then Clear else ShowBust;

State ShowStand: AddClk = Low;

Ace := Ace;

if (Restart == Low) then Clear else ShowStand;

State Zero: goto Clear;

@page

''test_vectors edited ...


Special Constants

Constant | Description
.C. | Clocked input (low-high-low transition)
.D. | Clock down edge (high-low transition)
.F. | Floating input or output signal
.K. | Clocked input (high-low-high transition)
.P. | Register preload
.SV# | # = 2 through 9. Drive the input to super voltage 2 through 9.
.U. | Clock up edge (low-high transition)
.X. | Don't care condition
.Z. | Tristate value

Special constants must be referenced with surrounding periods, and can be upper- or lowercase.

You can assign an identifier to a special constant to simplify entry. For example, declaring C = .C. allows you to use C without the surrounding periods to indicate the special constant value .C.


State Keyword (Declaration)

Syntax

state_id [, state_id ...] STATE [IN statereg_id ]

state_id - A symbolic state name to be referenced in a symbolic state description.

statereg_id - An identifier for a state register.

Purpose

The State declaration is made to declare a symbolic state name, and optionally associate it with a state register.

Use

If your design includes more than one symbolic state machine, use the IN keyword to associate each state with the corresponding state register.

Each state you declare corresponds to one flip-flop in a one-hot state machine.


State_diagram Keyword

Syntax

STATE_DIAGRAM state_reg
[-> state_out]
STATE state_exp : [equation]
[equation]
:
:
trans_stmt ;]

state_reg - An identifier or set of identifiers specifying the signals that determine the current state of the machine.

state_out - An identifier or set of identifiers that determine the next state of the machine (for designs with external registers).

state_exp - An expression giving the current state.

equation - A valid equation that defines the state machine outputs.

trans_stmt - An IF-THEN-ELSE, CASE, or GOTO statement, optionally followed by WITH transition equations.

Use

The state description describes the operation of a sequential state machine implemented with programmable logic. You can use state descriptions to describe logic as an alternative to Boolean equations or truth tables.

Example

The following is an example of a simple state machine that advances from one state to the next, setting the output to the current state, and then starting over again. Note that the states do not need to be specified in any particular order. Note also that state 2 is identified by an expression rather than by a constant. The state register is composed of the signals a and b.

state_diagram [a,b]

state 3: y = 3 ;
goto 0 ;

state 1: y = 1 ;
goto S2 ;

state 0: y = 0 ;
goto 1 ;

state S2; y = S2 ;
goto 3 ;


State Diagram Feedback in Equations

When you write equations not directly associated with the state diagram (in a separate equations section, for example) and want to decode the current state, you can use either .FB or .Q to refer to the fed-back state register values.

Using .FB is the simplest way to refer to feedback state register values. If you use .Q, you must consider whether 'invert' or 'buffer' was specified for the state registers, and invert the feedback signal accordingly.

Note If you specify both .Q and .FB, the dot extensions are merged during compilation.


State Diagram


State Diagram Example

State Diagram Example - Three-State Sequencer

The following design implements a simple sequencer that demonstrates the use of ABEL-HDL state diagrams. The number of state diagram states that can be processed depends on the number of transitions and the path of the transitions. For example a 64-state counter uses fewer terms (and smaller equations) than a 63-state counter. For large counter designs, use the syntax [CountA := CountA + 1] to create a counter rather than using a state machine.

Design Specifications

The following state diagram shows the transitions and the outputs. The state machine starts in state A and remains there until the start input goes high. It then sequences from state A to state B, from state B to state C, and back to state A. It remains in state A until start goes high again. If the reset input is high, the state machine returns to state A at the next clock cycle. If this reset to state A occurs during state B, a halt synchronous output goes high and remains high until start goes high.

During states B and C, asynchronous outputs 'in_B' and 'in_C' go high to indicate the current state. Activation of the hold input causes the machine to hold in state B or C until hold is no longer high or reset goes high.

Design Method

The sequencer is described by using a STATE_DIAGRAM section in the source file. Constants are declared to simplify the state diagram notation. The two state registers are grouped into a set called sreg and the three states (A, B, and C) are declared with appropriate values specified for each.

The state values chosen for this design allow the use of register preload to ensure that the machine starts in state A. For larger state machines with more state bits, careful numbering of states can dramatically reduce the logic required to implement the design. Using constant declarations to specify state values saves time when you make changes to these values.

The state diagram begins with the STATE_DIAGRAM statement that names the set of signals to use for the state register. In this example, sreg is the set of signals to use. Within the state diagram, if-then-else statements are used to indicate the transitions between states and input conditions that cause each transition. In addition, equations are written in each state that indicate the required outputs for each state of transition.

For example, state A reads:

State A:
in = 0;
in_C = 0;
if (start & !reset) then B with halt := 0;
else A with halt := halt;

This means that if the machine is in state A, and start is high but reset is low, it advances to state B. In any other condition, it remains in state A.

The equations for in_B and in_C indicate that those outputs should remain low while the machine is in state A. The equations for halt, specified using the with keyword, indicate that halt should go low if the machine transitions to state B, but should remain at its previous value if the machine stays in state A.

Test Vectors

The specification of the test vectors for this design is similar to other synchronous designs. The first vector is a preload vector to put the machine into a known state (A), and the following vectors exercise the functions of the machine. The A, B, and C constants are used in the vectors to indicate the value of the current state, improving the readability of the vectors.

3-State Sequencer Source File

module sequence

title 'State Machine example';

sequence device 'p16r4';

q1,q0 pin 14,15 istype 'reg,invert';

clock,enab,start,hold,reset pin 1,11,4,2,3;

halt pin 17;

in_B,in_C pin 12,13;

sreg = [q1,q0];

''State Values ...

A = 0; B = 1; C = 2;

equations

[q1,q0,halt].clk = clock;

[q1,q0,halt].oe = !enab;

state_diagram sreg;

State A: ''Hold in state A until start is active.

in_B = 0;

in_C = 0;

IF (start & !reset) THEN B WITH halt := 0;

ELSE A WITH halt := halt.fb;

State B: ''Advance to state C unless reset is active

in_B = 1; ''or hold is active. Turn on halt indicator

in_C = 0; ''if reset.

IF (reset) THEN A WITH halt := 1;

ELSE IF (hold) THEN B WITH halt := 0;

ELSE C WITH halt :+ 0;

State C: ''Go back to A unless halt is active.

in_B = 0; ''Reset overrides hold.

in_C = 1;

IF (hold & !reset) THEN C WITH halt := 0;

ELSE A WITH halt := 0;

''test_vectors edited...

end


State Machine Operation - BJACK

Operation of the state machine proceeds as follows if no aces are drawn:

  • If a card is needed - go to ShowHit.

  • When CardIn goes low - go to AddCard (Card values is added to score).

  • Wait until the card is taken from the reader.

  • Go to Test17 state.

  • If score is less than 17 take another card.

  • If the score is greater than or equal to 17 - go to state Test22.

  • If the score is less than 22 - go to ShowStand state.

  • If the score is 22 or greater - go to ShowBust state.

  • In either ShowStand or ShowBust state - go to Clear when Restart goes low.

  • When Restart goes high - return to ShowHit and cycle begins again.

Click here to see the state diagram.

Operation when an ace is drawn is essentially the same. If the card is an ace and no aces has been drawn previously, the state machine goes to state Add10, and ten is added to the count (effectively making the ace = 11). Transitions to and from Test17 and Test22 proceed as before. However, if the score exceeds 21 and an ace has been set to 11, the state machine goes to state Sub10, 10 is subtracted from the score, and the state machine goes to state Test17.


State_register Keyword

Syntax

statereg_id STATE_REGISTER ;

statereg_id - An identifier naming the state_register.

Purpose

For symbolic state diagrams, State_register declares a symbolic state machine name.


Supported ABEL Dot Extensions

Use the following tables to determine which ABEL dot extensions you can use with Xilinx CPLDs:

Pin-to-Pin Dot Extensions for CPLD Designs

Detailed Dot Extensions for CPLD Designs


Message Numbers 1000 to 1999

1000

1001

1002

1003

1004

1005

1006

1007

1008

1009

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021

1022

1023

1024

1025

1026

1027

1028

1029

1030

1031

1033

1034

1035

1036

1037

1038

1039

1040

1041

1042

1043

1044

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1046

1047

1048

1049

1050

1051

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1053

1054

1055

1056

1057

1058

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1060

1061

1062

1063

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1067

1068

1069

1070

1071

1072

1073

1074

1075

1076

1077

1078

1079

1080

1081

1082

1083

1084

1085

1086

1087

1088

1089

1091

1092

1093

1094

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1096

1097

1098

1099

1100

1101

1102

1103

1104

1105

1109

1110

1111

1112

1113

1114

1115

1116

1117

1118

1120

1121

1122

1124

1125

1126

1128

1129

1130

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1176

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1181

1182


Message Numbers 14000 to 14999

14000-14517 (BLIFOPT)

Command Line Error 14000: An Open-ABEL 2 file must be specified.

Run blifopt <input file> [options] to specify input file in Open-ABEL 2 format.

Fatal Error 14001: File name is too long.

Filenames containing more than eight characters are not supported.

Fatal Error 14002: Input file and output file are the same.

The output filename cannot be the same as the input filename.

Fatal Error 14003: Unable to open input file 'filename'.

The specified input file could not be opened. Ensure that the file exists, the path name is valid, and you have permission to access the file.

Fatal Error 14004: Unable to open output file 'filename'.

The specified output file could not be created. Ensure that the file exists, the path name is valid, and you have permission to write the file.

Command Line Error 14005: Can't specify both 'fixed' and 'choose'.

You must choose either 'Fixed' or 'Choose' for the Reduction Algorithm setting.

Command Line Error 14006: Can't specify both 'group' and 'bypin'.

You must choose either 'Group' or 'Bypin' for the Reduction Algorithm.

Message 14007: Deleting unused output 'xxx'.

Buried nodes that do not fan out are being removed.

Fatal Error 14008: Input wire 'wire' driven by more than one source.

More than one output is connected to the input. Check the functional block interconnection for invalid outputs.

Fatal Error 14009: Unable to create temporary file.

The temporary file cannot be created. Check for sufficient available disk space.

Warning 14010: Pre-Linked Group reduction is not supported in a hierarchical design 'design'.

Hierarchical designs must be linked before group reduction can occur.

Warning 14011: Pre-Linked DT reduction is not supported in a hierarchical design 'design'.

Hierarchical designs must be linked before D/T reduction can occur.

BLIFLINK

Fatal Error 14506: Signal 'xxx' of interface 'xxx' is not declared in the submodule.

The interface declaration port list includes a signal that is not declared in the submodule. All signals in the port list must be declared as pins in the submodule.

Logical Error 14509: Output 'xxx' in upper-level source 'xxx' can't be redriven to functional_block 'xxx'.

The output can only be connected to an upper-level pin and/or input of the functional_block.

Logical Error 14511: "Interface for 'xxx' does not match the interface declaration found in 'xxx'.

The interface declared at the higher-level source must match the interface declared at the lower-level source.

Logical Error 14512: Signal 'xxx' in module 'xxx' has an OE. An output wire is required for that signal.

A lower-level pin with an output enable must be declared in the port list and connected to a higher-level pin.

Fatal Error 14513: Cannot open file 'xxx'.

The specified input file could not be opened. Ensure that the file exists, the path name is valid, and you have permission to access the file.

Warning 14514: Signal 'xxx' in module 'xxx' floats so it is ignored.

The module contains a signal that is declared that will not be included in the expanded design. Reserve pins for future use in the top-level source file.

Fatal Error 14515: Design hierarchy forms a cycle.

Design logic contains a loop (A instantiates B, B instantiates C, C instantiates A) and cannot be expanded. Modify the design to break the loop.

Logical Error 14516: 'xxx' and 'xxx' form a cycle.

The instantiation of sources in the project create a loop. Check for sources that reference sources higher in the design hierarchy which reference the source.

Fatal Error 14517: Module 'xxx' does not exist.

The lower-level file was found, but did not contain the specified module name.


Message Numbers 17000 to 17999

BLIF2VLG

Fatal Error 17723: Cluster XXXX is declared both Port and Node.

The signal name XXX cannot be declared as both an I/O pin and an internal node. Doing so will generated a corrupted BLIF file.

Warning 17620: '!' ignored in xxx;

The '!' level indicator is being ignored in the indicated context.

Warning 17621: Signal XXXX was truncated at NNN characters

The signal name was truncated at the number of characters specified. Signal names are usually truncated to a maximum of 160 characters.

17600: Open-ABEL 2 file must be specified.

An Open-ABEL 2 file is required.

Fatal Error 17601: File name is too long.

Filenames cannot exceed a maximum of eight characters.

Fatal Error 17602: "Input file and output file are the same.

The input and output file names cannot be the same. Please specify distinct input and output file names.

Fatal Error17603: "Unable to open input file 'xxx'.

The specified input file cannot be opened by your computer's operating system.

Fatal Error 17604: "Unable to open output file 'xxx'.

The specified output file cannot be opened by your computer's operating system.


Message Numbers 18000 to 18999

BLIF to Netlist Messages (18800 to 18999)

Fatal Error 18806: Unable to open input file 'xxx'.

The specified input file cannot be opened.

Fatal Error 18807: Unable to open rulefile 'xxx'.

The specified file which is required for BLIF to Netlist cannot be opened. If this file is not present, contact Synario Technical Support.

Fatal Error 18808: Unable to open output file 'xxx'.

The specified output file cannot be opened. Verify that you have write access to specified drive and adequate disk space.

Fatal Error 18810: Unable to open vendor cell definition library 'xxx'.

The specified file which is required for BLIF to Netlist cannot be opened. If this file is not present, contact Synario Technical Support.

Fatal Error 18811: Unable to open vendor mapping library 'xxx'.

The specified file which is required for BLIF to Netlist cannot be opened. If this file is not present, contact Synario Technical Support.

Fatal Error 18812: Trouble reading rulefile 'xxx'.

Errors have been encountered in the rulefile. Contact Synario Technical Support.

Logical Error 18820: Output extension 'xxx' for signal 'yyy' not supported.

The specified dot extension is not supported by the target device. Often this message is an indication of problems with the design that have prevented the expected design normalization performed by diofft from occuring.

For example, "Output extension 'reg' for signal 'x.reg' not supported" generally means that there is no clock equation associated with signal 'x'. The specified dot extension is not supported by the target device.

Logical Error 18821: Input extension 'xxx' for signal 'yyy' not supported.

BLIF to Netlist may not support all input extensions (e.g. PIN) for all devices.

Logical Error 18822: Registered feedback 'xxx.Q' not supported for 'xxx.'

Registered feedback is not supported for combinational signals.

Logical Error 18823: Enable 'xxx.OE' is only allowed when top_level specified.

Output enables are only supported for pins of top level modules.

Logical Error 18824: Enable 'xxx.OE' is only supported for pins.

Output enables are only supported for output pins, not nodes.

Warning 18825: No logic associated with pin 'xxx'.

Pin 'xxx' is either an input pin which is not referenced (or whose reference has been optimized away) or an output pin which has never been assigned.

Warning 18826: No logic associated with node 'xxx'.

There is no logic associated with the specified node.

Logical Error 18827: Node 'xxx' is referenced but not set.

The specified node is referenced but has never been assigned.

Logical Error 18828: .D feedback for signal 'yyy' not supported.

BLIF to Netlist does not support .D feedback. Modify your ABEL-HDL design to reference combinational nodes.

Warning 18829: node 'xxx' is not referenced.

The specified node is never referenced in the design.

Logical Error 18830: No clock associated with registered signal 'xxx'.

Signal 'xxx' maps to a register but there is no clock associated with it. Modify your ABEL-HDL design to indicate the clock pin for the signal.

Logical Error 18831: Signal 'xxx' is missing either J or K dot extension.

A equation has been specified for either the J or the K extension but not for both.

Logical Error 18832: Signal 'xxx' is missing either R or S dot extension.

An equation has been specified for either the R or the S extension but not for both.

Logical Error 18835: Clock 'xxx.CLK' specified, but registered logic not present.

A clock connection is not supported for combinational logic.

Logical Error 18836: Latch enable 'xxx.LH specified, but latch logic not present.

A latch enable connection is not supported for combinational logic.

Logical Error 18837: Reset and/or preset specified for signal 'xxx', but registered logic not present.

Reset and preset connections are not supported for combinational logic.

Logical Error 18838: Clock enable 'xxx.CE' specified, but registered logic not present.

A clock enable connection is not supported for combinational logic.

Logical Error 18839: Enable 'xxx.OE' specified, but logic not present.

The only connection specified for the signal was the output enable connection.

Fatal Error 18840: Cell 'xxx' needed by signal 'yyy' is not supported by this device.

The mapping file does not include a mapping for cell 'xxx'. This is most likely because the device cannot implement generic cell 'xxx'. For example, if cell 'DPC' is not supported this is because the device does not support both a D-FF with both preset and clear.

Warning 18841: Combinational cycle detected. 'list of signals on cycle'

The design contains the specified combinational cycle.

Internal Errors 18900 to 18999:

Unexpected internal errors. Please contact Synario technical support.


Message Numbers 3507 to 3507

Message Numbers 3507 to 3509

Fatal Error 3507: cover verification failed

The logic defined by the output Equations is not functionally the same as the input Equation file.

Fatal Error 3508: outfile_name: malloc error

The Latte application ran out of memory.


Message Numbers 6000 to 6999

(Equation Simulator)

6002

6006

6007

6029

6030

6031

6032

6033

6034

6035

6036

6037

6038

6040

6041

6051

6052

6054

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Application Error -- Call to Undefined Dynalink

You may get this error message if Synario (or another Windows program) tried to load a Dynamic Link Library (DLL) file that did not contain the expected functions.


Test_vectors Keyword

Syntax

TEST_VECTORS [note]
(inputs -> outputs )
invalues -> outvalues ;
...

note - A string used to describe the test vectors.

inputs - An identifier or set of identifiers specifying the names of the input signals to the device, or feedback output signals.

outputs - An identifier or set of identifiers specifying the output signals from the device.

invalues - An input value or set of input values.

outvalues - An output value or set of output values resulting from the given inputs.

Special Constants

.C. | Clocked input (low-high-low transition)
.D. | Clock down edge (high-low transition)
.U. | Clock up edge (low-high transition)
.X. | Don't care condition
.Z. | Tristate value

These values may be used in ABEL test vectors.

Use

Test vectors specify the expected functional operation of a logic device by explicitly defining the device outputs as functions of the inputs. Test vectors are used for simulation of an internal model of the device and for functional testing of the programmed device.

Examples

Following is a simple test vector table:

TEST_VECTORS
( [A,B] -> [C,D] )
[0,0] -> [1,1] ;
[0,1] -> [1,0] ;
[1,0] -> [0,1] ;
[1,1] -> [0,0] ;

The following test vector table is equivalent to the table specified above because values for sets can be specified with numeric constants.

TEST_VECTORS
( [A,B] -> [C,D] )
0 -> 3 ;
1 -> 2 ;
2 -> 1 ;
3 -> 0 ;

If the signal identifiers in the test vector header were declared as active-low in the declaration section, then constant values specified in the test vectors will be inverted accordingly.


Test Vectors - BINBCD

The test vectors verify the operation of LT22 and GT16 by assigning various values for Score, checking the results

The test vectors for the BCD converter are defined by the following macro:

test_vectors ( score - [bcd2,bcd1])
clear (binary);
@repeat 32 { binary - [binary/10,binary%10];
inc(binary);}

This macro a test vector with variable binary set to 0 by the macro :

(a) {@const ?a=0};

followed by 31 vectors provided by the @repeat directive. The 31 vectors are generated by incrementing the value of the variable binary by 1 for each vector. On the output side of the test vectors, division is used to create the output for bcd2, while the remainder (modulus) operator is used to create the output for bcd1.


Test Vectors - BJACK

There are three sets of test vectors, each representing a different hand of play. The Restart function is used to set the design to a known state between each hand, and state identifiers are used instead of the binary values which they represent.


Test Vectors - MUXADD

The test vectors first clear the adder (Score = 0), then add card reader values 7 and 10. The Test vectors then input an ace (1) to produce a score of 1 and pull the is_Ace output high. Subsequent vectors verify the -10 function of the input multiplexer and adder. The trace statement lets you observe the carry signals in simulation.


Trace Keyword

Syntax

TRACE (inputs -> outputs) ;

Use

The TRACE statement is used to control the display features of the PLASim simulation module. TRACE statements can be placed before a test vector section, or imbedded within a sequence of test vectors.

Example

TRACE ( [A,B] -> [C ] );
TEST_VECTORS ( [A,B] -> [C,D] )
0 -> 3 ;
1 -> 2 ;
TRACE ( [A,B] -> [ D] );
2 -> 1 ;
3 -> 0 ;


Truth_Table Keyword

Syntax

TRUTH_TABLE ( inputs -> outputs )
invalues -> outvalues ;
or
TRUTH_TABLE ( inputs :> reg_outs )
invalues :> reg_outvalues ;
or
TRUTH_TABLE ( inputs :> reg_outs -> outputs )
invalues :> reg_outvalues -> outvalues ;

inputs - Input signal names to the logic function.

outputs - Output signal names from the logic function.

reg_outs - Registered (clocked) output signal names.

-> - Indicates the input to output function for combinational outputs.

:> - Indicates the input to output function for registered outputs.

Use

Truth tables specify outputs as functions of different input combinations in a tabular form. Truth tables are another way to describe logic designs with ABEL and may be used in lieu of (or in addition to) equations and state diagrams. A truth table includes a header describing the format of the table and the table.


Truth Table Examples

Truth Table Example - 7-Segment Display Decoder

This design illustrates the implementation of a 7-segment display decoder which uses a truth table to decode a 4-bit binary number and display the decimal equivalent on a 7-segment display.

Design Specification

The following block diagram shows a 7-segment decoder and the positions of the display segments. To light a segment, the corresponding line is driven low. When ena is low, the decoder is enabled. When ena is high, all outputs are driven to a high impedance state.

Design Method

The following figure shows the simplified block diagram of the design. The binary inputs and the decoder outputs are grouped into sets (bcd and led). The constants ON and OFF are declared so the design can be described in terms of turning a segment on and off. Because the outputs are active low, ON is declared as 0 and OFF is declared as 1.

The design is described in an equations section and a truth table section. The decoding function is described with a truth table that specifies the outputs required for each combination of inputs. The truth table header names the inputs and outputs. The body of the truth table defines the input to output function.

Because the design decodes a number to a 7-segment display, values for bcd are expressed as decimal numbers, and values for led are expressed with the constants ON and OFF; this makes the truth table easy to understand.

The input and output values could just as easily been described in another form. For example, the line in the truth table:

5 -> [ ON, OFF, ON, ON, Off, ON, ON]

could have been written in the equivalent form:

[0,1,0,1] -> 36

In the second equation the input value (5) is expressed in binary and the output (7 bits) are expressed in decimal notation (ON=0 and OFF=1). Either form of the equation is supported.

7-Segment Display Decoder Source File

module bcd7

title '7-segment display decoder 1'

'' a BCD to 7-Segment decoder similar to 7449

'' ---

'' f| g |b

'' ---

'' e| d |c

'' ---

bcd7 device 'P16P8'

D3,D2,D1,D0,Ena pin 2,3,4,5,6;

a,b,c,d,e,f,g pin 13,14,15,16,17,18,19 istype 'com';

bcd = [D3,D2,D1,D0];

led = [a,b,c,d,e,f,g];

ON,OFF = 0,1; ''for common anode LED displays

L,H,X,Z = 0,1,.X.,.Z.;

equations

led.oe = !Ena;

@dcset

truth_table (bcd -> [ a, b, c, d, e, f, g ])

0 -> [ ON, ON, ON, ON, ON, ON, OFF]

1 -> [ OFF,ON, ON, OFF,OFF,OFF,OFF]

2 -> [ ON, ON, OFF,ON, ON, OFF,ON ]

3 -> [ ON, ON, ON, ON, OFF,OFF,ON ]

4 -> [ OFF,ON, ON, OFF,OFF,ON, ON ]

5 -> [ ON, OFF,ON, ON, OFF,ON, ON ]

6 -> [ ON, OFF,ON, ON, ON, ON, ON ]

7 -> [ ON, ON, ON, OFF,OFF,OFF,OFF]

8 -> [ ON, ON, ON, ON, ON, ON, ON ]

9 -> [ ON, ON, ON, ON, OFF,ON, ON ]

''test_vectors edited

end


Using Intermediate Expressions

You can use intermediate (constant) expressions in the declarations section to reduce the number of output pins required to implement multi-level functions. Intermediate expressions can be useful when a module has repeated expressions. In general, intermediate expressions decrease the number of output pins required, but increase the amount of logic required per output

A constant expression is interpreted by the ABEL compiler as a string of characters, not as a function to be implemented. For example, for the following sets of Declarations and Equations

Declarations
TMP1 = [A3..A0] == [B3..B0];
TMP2 = [A7..A4] == [B7..B4];

Equations
F = TMP1 & TMP2;

the compiler directly substitutes the declarations into the equations, creating

F = (A7 !$ B7) & (A6 !$ B6) & (A5 !$ B5)
& (A4 !$ B4) & (A3 !$ B3) & (A2 !$ B2)
& (A1 !$ B1) & (A0 !$ B0);

In contrast, if you move the constant declarations into the equations section, in the following manner:

Declarations
TMP1,TMP2 pin 18,19

Equations
TMP1 = [A3..A0] == [B3..B0];
TMP2 = [A7..A4] == [B7..B4];
F = TMP1 & TMP2;

the compiler implements the equations as three discrete product terms. This will produce the following result:

TMP1 =(A3 !$ B3) & (A2 !$ B2) & (A1 !$ B1) &
 (A0 !$ B0);

TMP2 =(A7 !$ B7) & (A6 !$ B6) & (A5 !$ B5) & (A4 !$ B4);

F = TMP1 & TMP2;

The first example (using intermediate expressions) requires one output with 16 product terms. The second example (using equations) requires three outputs with less than 8 product terms per output. In some cases, the number of product terms required for both methods can be reduced during optimization.

Note An alternate method for specifying multi-level circuits such as this is to use the @CARRY directive.


Dot Extensions Used in the Left Hand Side of Equations

Dot Extension | Function Description | When Used With
 |  | Combinatorials | Registers
.ACLR | Device Independent Asynchronous Reset | Illegal | Recommended
.AP | Asynchronous Preset | Illegal | Allowed
.AR | Asynchronous Reset | Illegal | Allowed
.ASET | Device Independent Asynchronous RSet | Illegal | Recommended
.CE | Clock Enable1 | Illegal | Allowed
.CLK | Clock Input | Illegal | Recommended
.CLR | Device Independent Synchronous Reset | Illegal | Emulated
.D | D Flip-Flop2 | Illegal | Allowed
.DEC | Dual-edge Triggered Clock Input 4 | Illegal | Recommended
.FC | Flip-Flop Mode Control | Illegal | Illegal
.J | J Input to JK Flip-Flop | Illegal | Emulated
.K | K Input to JK Flip-Flop | Illegal | Emulated
.LD | Register Load Input | Illegal | Illegal
.LDG | DataGate Latch Enable (active-low)4 | Illegal | Recommended
.LE | Latch Enable - Active Low | Illegal | Emulated
.LH | Latch Enable - Active High | Illegal | Emulated
.OE | Output Enable3 | Recommended | Recommended
.PR | Register Preset | Illegal | Allowed
.R | R Input to SR Flip-Flop | Illegal | Emulated
.RE | Register Reset | Illegal | Allowed
.S | S Input to SR Flip-Flop | Illegal | Emulated
.SET | Device Independent Synchronous Preset | Illegal | Emulated
.SP | Synchronous Preset | Illegal | Emulated
.SR | Synchronous Reset | Illegal | Emulated
.T | T Input to T Flip-Flop | Illegal | Recommended

1 .CE is emulated for XC9500.
2 The recommended syntax for describing register D-inputs is using ":=" notation.
3 .OE is only allowed on chip level pins.

4. Applies to CoolRunner-II only.


Dot Extensions Used in the Right Hand Side of Equations

Dot Extension | Function Description | When Used With
 |  | Input Only Pins | Registered Nodes | Registered Output Pins | Combinatorial Nodes | Combinatorial Output Pins
.COM | Combinatorial Feedback (from register data input) | Illegal | Emulated | Emulated | Illegal | Recommended
.D | Combinatorial Feedback from Register Data Input | Illegal | Emulated | Emulated | Illegal | Illegal
.FB* | Register Feedback | Illegal | Allowed | Recommended | Illegal | Illegal
.PIN | Pin Feedback | Allowed** | Illegal | Recommended | Illegal | Recommended
.Q* | Register Feedback | Illegal | Allowed | Allowed | Illegal | Illegal
None | Input or Node Feedback | Recommended | Recommended | Allowed*** | Recommended | Allowed***

* .FB always represents the non-inverted feedback of the signal. .Q feedback is inverted if istype'invert' is also used.
** If you use .PIN on an input only signal, you must use it on all occurrences of that signal.
*** Such cases are ambiguous and typically result in pin feedback.


When-Then-Else Keyword

Syntax

[ WHEN condition THEN ] [!]
 element=expression
 ;
[ ELSE equation ];
-or-
[ WHEN condition THEN ] equation ;
[ ELSE equation ];

condition - Any valid expression.

element - An identifier naming a signal or set of signals, or an actual set, to which the value of the expression will be assigned.

expression - Any valid expression.

Use

This statement is used in equations. Equations use the four assignment operators = and ?= (combinational or detailed), and := and ?:= (registered pin-to-pin).

Note Equation blocks used within a conditional expression such as When-Then-Else result in logic functions that are logically ANDed with the conditional expression that is in effect.

Caution: When-Then-Else is only supported in equations. Use If-Then-Else for state diagrams.

Example

WHEN B THEN A=B;
ELSE A=C;

WHEN (Mode == S_Data) THEN { Out_data := S_in;
S_Valid := 1;
}
ELSE WHEN (Mode == T_Data) THEN { Out_data := T_in;
T_Valid := 1;
}


With Keyword

Syntax

trans_stmt state_exp WITH { equation
[equation]
}

trans_stmt - The IF, ELSE, or CASE statements.

state_exp - The next state.

equation - An equation for state machine outputs.

Use

The With statement is used in the State_diagram section. When used in conjunction with the If-then or Case statement, it allows output equations to be written in terms of transitions.

Note The endwith keyword is supported for backward compatibility.

Example

state 5 : IF a == 1 then 1
WITH {x := 1 ;
y := 1 ;}
ELSE 2 WITH {x := 0 ;
y := 1 ;}


Xilinx ABEL Property Statements

Xilinx property statements are the mechanism by which the ABEL7 compiler passes device-specific information to the Xilinx CPLD fitter. The ABEL7 compiler does not look at the content of these statements.

BUFG | IOSTANDARD | PULLUP
COOL_CLK | KEEPER | SCHMITT_TRIGGER
FAST | LOC | SLOW
INIT | OPEN_DRAIN | TNM
INREG | PWR_MODE |


xilinx property BUFG

Use BUFG to assign signals to Xilinx CPLD global nets with the following syntax:

xilinx property 'BUFG={CLK|OE|SR} signal_list';

CLK, OE, and SR indicate clock, output enable, or set/reset respectively.
For example, if you want to assign signals to the global clock nets, do the following:

xilinx property 'BUFG=CLK clk0 clk1';

To assign signals to the global output enable nets, do the following:

xilinx property 'BUFG=OE oe0 oe1';

To assign a signal to the XC9500 global set/reset net, do the following:

xilinx property 'BUFG=SR reset';


xilinx property COOL_CLK

Syntax

XILINX PROPERTY 'COOL_CLK signal_name';

Example

XILINX PROPERTY 'COOL_CLK mysignal';

Families

CoolRunner-II.

Description

Power savings can be increased by combining clock division circuitry with the DualEDGE circuitry. This capability is called CoolCLOCK and is designed to reduce clocking power within the CPLD. Because the clock net can be an appreciable power drain, the clock power can be reduced by driving the net at half frequency, then doubling the clock rate using DualEDGE triggered macrocells.

Applies to any input pad or internal signal driving a register clock.

Applying COOL_CLK to a clock net is equivalent to passing the clock through a divide-by-two clock divider (CLK_DIV2) and replacing all flops controlled by that clock with DualEDGE flops. Using the COOL_CLK attribute does not alter your overall design functionality.

Restrictions:

You can't use COOL_CLK on a clock that triggers any flop on the low-going edge. (The CoolRunner-II clock divider can only be triggered on the high-going edge of the clock signal.)

If there are any DualEDGE flops in your design source, the clock that controls any of them cannot be specified as a COOL_CLK.

If there is already a clock divider in your design source, you cannot also use COOL_CLK. (CoolRunner-II devices contain only one clock divider.)


xilinx property FAST

Use FAST to selectively select fast slew rate on a pin-by-pin basis for any output or I/O signal. The default slew rate for the design is controlled in the Design Manager. Use the following syntax:

xilinx property 'FAST signal_list';

For example, to set selective pins to fast slew rate, use the following:

xilinx property 'FAST out0 out1';

The remaining pins, if not listed in the signal list of a SLOW property statement, will assume the default slew rate specified in the Design Manager


xilinx property INIT

Use INIT to control the initial value of macrocell registers during device power up.

For XC9500 devices, use this property for registers that must power up to a logic 1 state (by default these registers power up in a 0 logic state) and you don't have any logic signal available to place these registers into that state. Use the following syntax:

xilinx property 'INIT={S|R} signal_list';

S and R indicate logic 1 and logic 0 respectively.

For example, if you want to initialize selected registers to 1 use:

xilinx property 'INIT=S count0 count1 count2';

To initialize selected registers to 0 use:

xilinx property 'INIT=R count0 count1 count2';

Note It's best to drive XC9500 registers to a known state with the global GSR signal.

Note Because this value is only passed onto the fitter, and not used by the ABEL7 compiler, the initial value will not be reflected in the functional simulation.


xilinx property INREG

Syntax

XILINX PROPERTY 'inreg mysignal';

Families:

XPLA3, CR-II.

Description

Applies to register and latch instances with their D-inputs driven by input pads, or to the Q-output nets of such registers/latches.


xilinx property IOSTANDARD

Syntax

XILINX PROPERTY 'iostandard=value IO_pad_name';

Legal values (XC9500XV): LVTTL (default), LVCMOS2, X25TO18.

Legal values (CoolRunner-II): LVTTL, LVCMOS15, LVCMOS18, LVCMOS25, LVCMOS33, HSTL_I, SSTL2_I, SSTL3_I. The default can be set in the Project Navigator interface by highlighting Implement Design in the processes window, then selecting Process --> Properties. The Process Properties dialog box will appear. Select the Basic tab. You will see Output Voltage Standard at the bottom. Click on this box and select from the available standards.

Example

XILINX PROPERTY 'iostandard=SSTL3_I mysignal';

Families

XC9500XV, CoolRunner-II.

Description

Applies to output and I/O pads. IOSTANDARD is a basic mapping constraint and synthesis constraint.

You can apply IOSTANDARD to outputs of XC9500XV devices to specify the VCCO voltage.

The X25TO18 setting is provided for generating 1.8V compatible outputs from a CPLD normally operating in a 2.5V environment. Output pads of XC9500XV devices are grouped into banks, each supplied by a VCCO pin.

The software automatically groups outputs with similar IOSTANDARD settings into the same bank when no location constraints are specified.

IOSTANDARD is illegal when attached to a net or signal except when the net or signal is connected to a pad. In this case, IOSTANDARD is treated as attached to the pad instance. When attached to a design element, IOSTANDARD propagates to all applicable elements in the hierarchy within the design element.


xilinx property KEEPER

Syntax

XILINX PROPERTY 'KEEPER signal_name';

Example

XILINX PROPERTY 'KEEPER mysignal';

Families

CoolRunner-II.

Description

KEEPER is a basic mapping constraint. It retains the value of the output net it is attached to. For example, if logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the net driver is then tristated, KEEPER continues to drive a weak/resistive 1 onto the net.

The KEEPER constraint must follow the same banking rules as the KEEPER component. See the Libraries Guide for information on the banking rules.

Applies to tristate and open-drain output and I/O pads. Also applies to input-only pads.


xilinx property LOC

Use the BLOCK property to pass the LOC constraint to control logic placement in Xilinx CPLDs. To assign a node to a particular function block, use:

xilinx property 'BLOCK signal_name LOC=FBn'

where n is the function block number. For example, to assign node xyz to function block 7 use:

xilinx property 'BLOCK xyz LOC=FB7'

To assign a node to a specific macrocell use:

xilinx property 'BLOCK signal_name LOC=FBn_m'

where n is the function block number and m is the macrocell number as defined in the data sheet. For example, to assign node xyz to function block 7, macrocell 1, use:

xilinx property 'BLOCK xyz LOC=FB7_1

Since ABEL does not allow alphanumeric pin locations, LOC can also be used to assign pinouts for PGA and BGA packages. For example, to assign signal xyz to pin A2, use:

xilinx property 'BLOCK xyz LOC=A2';

Note You can only specify one signal name per BLOCK property statement.


xilinx property OPEN_DRAIN

Syntax

XILINX PROPERTY 'OPEN_DRAIN IO_pad_name';

Examples

XILINX PROPERTY 'OPEN_DRAIN mysignal';

Families

CoolRunner-II.

Description

Applies to non-tristate output or to tristate output in which the data input to the output buffer is dangling or driven by constant 0 (GND). The output buffer will be configured as open-drain. When applied to a non-tristate output, the output is converted to an open_drain so that a one state on the design signal produces a high-Z on the device pin.


xilinx property PULLUP

Syntax

XILINX PROPERTY 'PULLUP IO_pad_name';

Example

XILINX PROPERTY 'PULLUP mysignal';

Families

CoolRunner XPLA3 (inputs only), CoolRunner-II.

Description

PULLUP is a basic mapping constraint. It guarantees a logic High level to allow tristated nets to avoid floating when not being driven.

Applies to tristate and open-drain output and I/O pads (CoolRunner-II only). Also applies to input-only pads (XPLA3 and CoolRunner-II).

PULLUP on a non-tristate output will be ignored.

PULLUP and KEEPER cannot be used in the same design; PULLUP will be interpreted as KEEPER.

PULLUP found on a non-input pin will be ignored.


xilinx property PWR_MODE

Use PWR_MODE to selectively control whether specified logic operates in high speed or low power mode. The default power mode for the design is controlled in the Project Manager. Use the following syntax:

xilinx property 'PWR_MODE={LOW|STD} signal_list';

For example, to set selective functions to low power mode rate, (the remaining functions use the default power mode) use the following:

xilinx property 'PWR_MODE=LOW out0 out1';

For example, to set selective functions to high speed mode, (the remaining functions use the default power mode) use the following:

xilinx property 'PWR_MODE=STD out0 out1';


xilinx property SCHMITT_TRIGGER

Syntax

XILINX PROPERTY 'SCHMITT_TRIGGER signal_name';

Example

XILINX PROPERTY 'SCHMITT_TRIGGER mysignal';

Families

CoolRunner-II.

Description

Applies to all input pads.

Each input can selectively arrive through SCHMITT_TRIGGER inputs. This adds a small time delay, but substantially reduces noise on that input pin. This also allows easy generation of external clock circuits.

This property selects the schmitt trigger input buffer on the device. This property does not select the amount of hysteresis, only the enabling or disabling of the input hysteresis feature.


xilinx property SLOW

Use SLOW to selectively select slow slew rate on a pin-by-pin basis for any output or I/O signal. The default slew rate for the design is controlled in the Design Manager. Use the following syntax:

xilinx property 'SLOW signal_list';

For example, to set selective pins to slow slew rate, use the following:

xilinx property 'SLOW out0 out1';

The remaining pins, if not listed in the signal list of a FAST property statement, will assume the default slew rate specified in the Design Manager


xilinx property TNM

Use TNM to tag flip-flops with a timing-group name to be used in a Timespec.

XILINX PROPERTY 'TNM=group_name signal_name ...';

Where signal_name is the name of a registered node or output pin signal in your design.

Note If you assign the TNM property to a registered output signal, the fitter will apply it to the flip-flop driving the signal, not the output pad itself.

To assign group names to input and output pads in your top-level ABEL design, use the TNM or TIMEGRP property in the UCF file. For ABEL modules in a schematic design, you can declare group names for your input and output pads in your schematic.


Xor_Factors Keyword

Syntax

XOR_FACTORS

signal_name = xor_factors ;

Use

The XOR_Factor section allows you to specify a Boolean expression that is to be factored out of (and XORed with) the sum-of-products reduced equations. This can result in dramatic reductions in the size of the reduced equations. The XOR_Factor feature is a technique for converting a sum of products (SOP) equation into an exclusive OR (XOR) equation. The resulting equation contains the sum of product functions that, when exclusive ORed together, have the same function as the original. The XOR_Factor equation will be divided into the original equation, with factor (or its complement) on one side of the XOR and the remainder on the other side.

Example

For the following equations,

!Q16 = A & B & !D
# A & B & !C
# !B & C & D
# !A & C & D

a useful XOR_Factor would be

XOR_Factors

Q16 = A & B;


ABEL WYSIWYG Option

The WYSIWYG option causes logic in your design to be optimized primarily according to how you write your equations in your ABEL design source file. As a result, you can influence the way the fitter performs logic optimization by altering the way you express your logic in your source design. For example, you can break a complex equation into selected intermediate nodes to get the fitter to break multi-level logic functions between macrocells the way you prefer.

Note First, the WYSIWYG feature causes all nodes defined in your source design to be preserved throughout the compilation phase and into the design netlist. The synthesis compiler itself does not optimize any logic across your equation boundaries. The WYSIWYG option then forces the CPLD Fitter to map all logic within each original ABEL equation into the same macrocell, if physically possible. That means all logic trees bounded by primary inputs and outputs (pins and registers) and by the nodes declared in your design are fully collapsed, regardless of the Collapsing Pterm and Input Limit value. The Fitter will then continue to perform normal logic optimization and collapsing across equation boundaries throughout the design, up to the specified Collapsing Pterm and Input Limit values, unless otherwise constrained by KEEP or RETAIN attributes in your design. Arithmetic inferencing is automatically disabled when WYSIWYG is turned on.

When the WYSIWYG option is off (default) all logic from your ABEL design is subject to optimization by XST synthesis. Original equation boundaries and names of combinatorial nodes are generally not preserved.

The WYSIWYG option is supported only for pure ABEL designs when the ABEL-XST flow is selected as the project's Synthesis Tool. To enable it, highlight your top-level ABEL source module, highlight the Implement Design process and select Process -> Properties. Then set the value of the WYSIWYG property in the Synthesis tab to "ABEL".


Creating Bidirectional Signals Using ABEL

The following code shows how to implement bidirectional signals in ABEL:

out0:= out0.pin; `` clock data on pin into register
out0.clk = strobe0; `` on rising edge of strobe0
out0.oe = read; `` Read back when read is high
out1:= out0.q $ out0.pin; `` out1 goes high when out0 register
out1.clk = strobe1; `` and pin are different

The following drawing shows how this code is implemented in the device:


Creating Counters Using ABEL

The following equations show how to implement up, down, and bidirectional counters:

EQUATIONS;

// Up Counter
upcount := (upcount.q + 1) & up & !reset ``Count up.
# upcount.q & !up & !reset; ``Hold clear if reset is high.
upcount.clk = clock;

// Down Counter
dncount := (dncount.q - 1) & dn & !reset ``Count down.
# dncount.q & !dn & !reset; ``Hold Clear if reset is high.
dncount.clk = clock;

// Bidirectional Counter
bicount := (bicount.q + 1) & up & !reset ``Count up.
# (bicount.q - 1) & dn & !reset ``Count down.
# bicount.q & !up & !dn & !reset;
``Hold Clear if reset is high.
bicount.clk = clock;


Creating Latches in ABEL

The following code shows how to create registered and combinatorial latches using ABEL.

// Registered Latches
out0 node istype `reg';
Equations
out0 := data0;
out0.lh = latch_enable; `` transparent high

// Combinatorial Latches
out0 node istype `com, retain';
`` retain attribute turns off Boolean minimization in
`` ABEL compiler and CPLD fitter to retain redundant
`` product terms

out = data & latch `` latch is transparent high
# out & !latch `` latch data on falling edge
# out & data; `` redundant product term


Creating Readback Registers in ABEL

The following code shows how to create a readback register using ABEL:

data_reg.clk = clock; `` Clock register with system clock
data_reg.oe = read_enable; `` Enable output when reading
data_reg.d = data_reg.pin; `` Write data on pin into register
data_reg.ce = write_enable; `` when write enable is active


Multiplexing Output Signals in ABEL

The following code shows how to multiplex signals in ABEL:

// Implementing output multiplexer
 using 3-state control
dout0 := data0;
dout1 := data1;
dout0.oe = select; `` tie dout0 and dout1 output
 pins together
dout1.oe = !select;
// Implementing output multiplexer in a macrocell
dout = data0 & select
# data1 & !select;
// Registered output multiplexer for faster tCO
dout := data0 & select
# data1 & !select;


ABEL Design Flow

This tutorial demonstrates how to create an ABEL design by walking you through a design that has already been created for you.

The major steps for creating an ABEL design are:

A - Opening the project.

B - Preparing the jc2_abl Design.

C - Fitting the design.

D - Simulating the design.

E - Programming a device.

Continue With Opening The Project


Open the jc2_sabl ABEL Macro

The ABEL macro, Jcounter.abl contains some of the logic of the jc2_abl design. In this step we will synthesize the logic and create a macro symbol to put in the schematic.

  1. To open the ABEL design that we have created for you, click File -> Open. The Open dialog box will appear. Select the jcounter.abl file.

The following HDL Editor screen appears within the Project Navigator, showing the complete code for the ABEL macro:

Note that the jcounter.abl source appears under the jc2_top design in the Sources window.

  2. Synthesize this ABEL macro by highlighting the jc2_top design in the Sources window, then double-clicking Synthesize in the Processes window.

When the synthesis finishes, a check mark will appear before the Synthesize process.

Note The Jcounter.abl file has not been added to the project. Therefore, the synthesizer will not include top level input and output pads for this macro. Instead the top level schematic, which contains the Jcounter macro, will include all top level input and output pads required for implementation.

  3. You can now create the macro symbol for the schematic selecting jcounter in the Sources window, then double-clicking Create Schematic Symbol in the Processes window.

Note The installed jc2_sabl schematic already contains this macro symbol.

The ABEL macro is now available, as a symbol named Jcounter, from within the schematic editor.

Continue With Opening The Schematic


Schematic Design Flow - With an Embedded ABEL Macro

This tutorial demonstrates how to embed an ABEL macro into a schematic.

Note It's usually a good idea to create the ABEL macro first because it will become a component (symbol), available from within the schematic editor.

The major steps for creating a schematic design with an embedded ABEL macro are:

A - Opening the project.

B - Opening the ABEL macro.

C - Opening the schematic.

D - Implementing the design.

E - Programming a device.

Continue With Opening The Project


Simulating an ABEL Design

Note The Implement Design process must be run before simulation can be run.

  1. To display the simulation processes, click once on jc2_top-vectors. The processes will display as shown below. Note Click the + sign adjacent to Translate Test Vectors to display as shown.

  2. Double-click Translate Test Vectors. This will run the processes Compile Test Vectors and Generate VHDL Test Bench. After the test vectors compile, the success will be shown by green check marks.

  3. To activate the ModelSim Simulator for Post-Fit VHDL simulation, highlight Simulate Post-Fit VHDL Model and select Process -> Run from the menu bar. The ModelSim trademark appears, followed by ModelSim selected ModelSim dialog boxes (selected under the Display Options tab). For information about ModelSim considerations, see ModelSim Considerations. For detailed information about ModelSim, see the online help from the ModelSim interface.

  4. Click Run ModelSim. ModelSim will bring up several windows. To display the waveforms as shown below, use the zoom in and zoom out icons until the clk waveform displays. Then, click on the plus sign (+) adjacent to the q bus (/testbench/q in the display) to display the individual waveforms.

Note The simulation is set to run for 1000 ns. If you would like to set a different run time, go back to step two and set the run time as you want. If you want to run the simulation continuously, use the run icons found on the ModelSim wave display (shown above). The icons are Run, Continue Run, Run -all, and Break.

  5. Double-click View VHDL Simulation Report to view the report VHDL report. Double-click View Blif Simulation Report to view the Blif Report.

Back to Design Flow Tutorials

Continue with Device Programming - Downloading Your Design File


Simulating a New ABEL Design

  1. To simulate an ABEL design you can either include ABEL style test vectors in your ABEL design source or create a VHDL test bench (if you are using the ABEL XST VHDL flow) or a Verilog test fixture (if you are using the ABEL XST Verilog flow). If your design contains ABEL style test vectors, they will be translated into a VHDL or Verilog test bench automatically. Either way, your design will be simulated using an HDL simulator (ModelSim) supported by iSE. Both functional (pre-route) and timing (post-route) simulation is available. The process for creating a VHDL or Verilog test bench for an ABEL design is similar to VHDL and Verilog designs. This page describes the process for including and translating ABEL style test vectors in your source design.

  2. The Sources in Project listing shows the presence of vectors. Highlight the vectors icon (my_mod.abv) to display simulation processes.

  3. Double-click Translate Test Vectors in the processes window to compile the test vectors and generate a test bench.

  4. Double-click Simulate Behavioral VHDL Model to run the simulation. The ModelSim start window will appear. Click Run ModelSim.

  5. ModelSim will bring up several windows. To display the waveforms as shown below, use the zoom in and zoom out icons until the clk waveform displays. Then, click on the plus sign (+) adjacent to the q bus (/testbench/q in the display) to display the individual waveforms.

Note The simulation is set to run for 1000 ns. If you would like to set a different run time, go back to step two and set the run time as you want. If you want to run the simulation continuously, use the run icons found on the ModelSim wave display (shown above). The icons are Run, Continue Run, Run -all, and Break.

  6. Double-click Equation Simulation Report to view the report. Double-click View Blif Simulation Report to view the Blif Report.

Continue with Programming Example


Assigning Pins through XABEL

Assigning Pins through ABEL

The following example shows how to add pin assignments using XABEL.

a pin 34;
b pin 35 istype `reg';

XABEL only accepts numeric pin numbers. If you are using a BGA package (which uses alphanumeric pin designations), then you must use a UCF file to lockdown the pins.


Implementing Counters Using ABEL

The following equations show how to implement up, down, and bidirectional counters using ABEL.

// Up Counter

Up count :=(upcount.q + 1) & up & !reset "Count up.

# upcount.q$ !reset, "Hold clear is reset is high.

Upcount.clk = clock;

// Down Counter

dncount := (dncount.q - 1) & dn & !reset "Count down.

# dncount.q & !dn & !reset; "Hold Clear if reset is high.

dncount.clk = clock;

// Bidirectional Counter

bicount := (bicount.q + 1) & up & !reset "Count Up

# (bicount.q - 1) & dn & !reset

# bicount.q & !up & !dn & !reset;

"Hold Clear if reset is high.

bicount.clk = clock


Creating Bidirectional Signals Using ABEL

The following code shows how to implement bidirectional signals using XABEL.

out0:= out0.pin; " clock data on pin into register
out0.clk = strobe0; " on rising edge of strobe0
out0.oe = read; " Read back when read is high
out1:= out0.q $ out0.pin; " out1 goes high when out0 register
out1.clk = strobe1; " and pin are different

The following figure shows how this code implements in the device.


Implementing Flip-Flops with Clock Enable Using ABEL

The following ABEL code demonstrates how to implement flip-flops with clock enable. In this example, Q-OUT is the output of the register, EN is the clock enable signal, D_IN is the D input of the register, and CLK is the clock signal

Declarations

D_IN pin;

CLK pin;

EN pin;

Q_OUT pin istype 'reg';

Equations

Q_OUT.clk = CLK;

Q_OUT := D_IN;

Q_OUT.ce= EN;


Implementing Flip-Flops with Asynchronous Preset or Reset Using ABEL

The following ABEL code demonstrates how to implement flip-flops with asynchronous reset.

Declarations

DIN pin;

CLK pin;

RESET pin;

DOUT pin istype 'reg';

Equations

DOUT.CLK = CLK;

DOUT.AR = RESET;

DOUT := DIN

The following ABEL code demonstrates how to implement flip-flops with asynchronous preset.

Declarations

DIN pin;

CLK pin;

RESET pin;

DOUT pin istype 'reg';

Equations

DOUT.CLK = CLK;

DOUT.AP = RESET;

DOUT := DIN


Implementing Slew Rates Using ABEL

You can control slew rate for specific output or I/O pins with the FAST and SLOW attributes in XABEL. Use these attributes to selectively control whether specific pins operate in fast slew rate (FAST) or slew rate limited (SLOW) mode.

The following example demonstrates attributes in XABEL.

xilinx property `SLOW q1 q2 q3';
xilinx property `FAST q4';


Implementing One-hot Encoded State Machines Using XABEL

Implementing One-Hot Encoded State Machines Using ABEL

You can achieve a one-hot encoded state machine by writing a symbolic state machine in XABEL. Rather than defining an encoding scheme for each state, give a name to each state, and the compiler assigns a register to each state.

module one_hot
Title 'one_hot'

Declarations

a PIN;
b PIN;
c PIN;
clk PIN;
outputs2..outputs0 PIN;
outputs = [outputs2..outputs0];

sbit STATE_REGISTER istype 'reg_d';
s1, s2, s3 STATE;

Equations

sbit.clk = clk;
sl.ap=0; "Creates a preset condition on the initial
"state to ensure a proper power-up state.

State_Diagram sbit

State s1: outputs = [0,0,0];
if a then s2;
else s1;
State s2: outputs = [0,1,0];
if b then s3;
else s2;
State s3: outputs = [1,1,1];
if c then s1;
else s3;

end one_hot;


Implementing a Combinatorial Multiplexer Using ABEL

The following ABEL code demonstrates how to implement a combinatorial multiplexer.

" 4 to 1 multiplexer design

" SEL0..SEL1 pin;

" A,B,C,D pin;

" MUX_OUT pin istype 'com';

"

" SEL = [SEL1,SEL0];

equations

when SEL==0 then MUX_OUT = A;

else when SEL==1 then MUX_OUT = B;

else when SEL==2 then MUX_OUT = C;

else when SEL==3 then MUX_OUT = D;


ABEL Istypes

'bidir'

'default_0'

'default_1'

'feed_or'

'feed_pin'

'feed_reg'

'input'

'output'

'reg_JKD'

'reg_L'

'reg_RS'

'buffer'

'collapse'

'com'

'dc'

'invert'

'keep'

'neg'

'pos'

'reg'

'reg_D'

'reg_G'

'reg_JK'

'reg_SR'

'reg_T'

'retain'

'xor'


ABEL Reserved Words

async_reset

bus

case

declarations

device

else

enable

end

equations

external

flag

functional_block

fuses

goto

group

if-then-else

interface

istype

library

macro

module

node

options

partition

pin

place

place_input

property

signal

state

state_diagram

state_register

sync_reset

test_vectors

then

title

trace

truth_table

when-then-else

with

xor_factors


Creating ABEL Test Vectors

You can create ABEL test vectors to describe input stimulus and the expected outputs for logic simulation. The test vector format is similar to an ABEL truth table format. The formatting consists of a header describing the inputs and outputs followed by corresponding numerical values or special constants describing the input and output values.

What to do First

Open the project for which you want to create a new test vector.

To Create a New Test Vector

  1. Select Project > New Source to open the New dialog box.

  2. Select ABEL Test Vector from the list of available source types.

  3. Enter a name for the new test vector in the File Name field.

  4. Enter the directory name in the Location field, or browse to the directory in which the new source will reside.

  5. Check the Add to Project checkbox if you want to add this test vector automatically to the project.

  6. Click Next. The New Source Information window opens to display a summary of the new test vector.

  7. Click Finish.

What to Expect

  • If you checked Add to Project, the test vector has been automatically added to the project.

  • You will see the new test vector file, file_name.abv, with the file name you provided in the Sources in Project window.


Creating an ABEL-HDL Module

You can create an ABEL-HDL Module as a source for your design.

What to do First

Open the project for which you want to create a new ABEL-HDL module.

To Create an ABEL-HDL Module

  1. Select Project > New Source to open the New dialog box.

  2. Select ABEL-HDL Module from the list of available source types.

  3. Enter a name for the new test vector in the File Name field.

  4. Enter the directory name in the Location field, or browse to the directory in which the new source will reside.

  5. Check the Add to Project checkbox if you want to add this test vector automatically to the project.

  6. Click Next. The Define ABEL-HDL Sources window opens. Use this window to define the ABEL-HDL module.

  7. Click Next. The New Source Information window opens to display a summary of the new test vector.

  8. Click Finish.

What to Expect

  • If you checked Add to Project, the module has been automatically added to the project.

  • You will see the new module file, file_name.abl, with the file name you provided in the Sources in Project window.


ABEL

Advanced Boolean Expression Language (ABEL) is a high-level language (HDL) and compilation system produced by Data I/O Corporation.


ABEL HDL File

The ABEL-HDL (ABL) file is a file written in ABEL Hardware Description Language that contains logic expressed as equations, truth tables, and state machine descriptions.


Define ABEL-VHDL Source

Define ABEL-HDL Source

  1. Enter a pin name in the Pin Name field.

  2. Click in the MSB (most significant bit) field and set the desired value.

  3. Click in the LSB (least significant bit) field and set the desired value.

The values set in the MSB and LSB fields define the signal on the pin name as a bus.

For example, for the pin named DATA with an MSB of 7 and an LSB of 0, the bus would be DATA[7:0].


Xilinx ABEL

Xilinx ABEL is a design entry package consisting of a Xilinx-specific version of the ABEL design entry software and a series of translation programs. It uses Boolean equations, truth tables, and state machines to create modules and full designs for CPLDs and modules for FPGAs.


Define ABEL-HDL Source Dialog Box

Use this dialog box to define an ABEL HDL source file created in the New Source dialog box. This dialog box displays after you create a new source file for a project with a CPLD device and ABEL XST device-design flow specified (for example, AUTO-PC 9500 - ABEL XST). This dialog box is followed by the New Source Information dialog box.

Note "ABEL_HDL Module" must be selected as the source type to bring up this dialog box.

Module Name

Enter a module name. The wizard creates a skeleton ABEL module with the specified name. By default, this field contains the base file name of the source.

Note If a module name is not provided (if you erase the default one), Project Navigator simply creates a blank ABEL file.

Pin Name

Enter a pin name. The skeleton ABEL file contains PIN declarations for each of the defined pins.

MSB and LSB

Define the signal on the pin name as a bus. For example, for a pin named DATA with an MSB of 7 and an LSB of 0, the bus is DATA[7:0].

Note If the signal on the pin is not a bus (for example, a clock), leave the MSB and LSB fields blank.

MSB

Enter a value for the Most Significant Bit.

LSB

Enter a value for the Least Significant Bit.


Running the TDO to ABEL Converter

You can convert a Text Design Output (.TDO) file to ABEL language. A (.TDO) file is an ASCII text file that contains the ABEL HDL (AHDL) equivalent of the fully optimized logic for a device in your project.

TDO files facilitate back-annotation and preserve the existing logic synthesis in your project.

What to do First

Click on the targeted Device entry (for example, xc9572xl-5cs48) in the Sources in Project window.

To TDO to ABEL Converter

Double-click on TDO to ABEL Converter process under the Design Entry Utilities toolbox.

What to Expect

You will need to manually add the converted file to your project.

Properties

Default property values are used for this process unless you modify them. You can set the TDO to ABEL options in the Process Properties dialog box.

What to do Next

Run the implement design process.


TDO to ABEL Options

TDO to ABEL

The TDO Input File property applies to the TDO to ABEL Converter process. This property specifies the Text Design Output (TDO) file that you want converted to ABEL file format.

Enter the location and file name of the TDO file you want converted, or click the browse button and browse to your TDO file in the Select dialog box.


label

VHDL Reserved Word: label

Purpose

An entity class, to be stated during attribute specification of user-defined attributes.

Syntax

entity_specification ::= entity_name_list; entity_class

entity_class ::=
entity | architecture | configuration
| procedure | function | package
| type | subtype | constant
| signal | variable | component
| label | literal | units
| group | file

Example

attribute placement of n1: label is (50,45);