Notes on I2C Bus FPGA Design

I2C is a shared bus with the following properties

• multi-master operation, ie any device could become master.
• all I2C devices share only 2 signals : clock and bi-directional data
• each device has its own address, called device address

Notes

1. START : is in the case when SCK is high and SDA is going low;
2. STOP : is in the case when SCK is high and SDA is going high;
3. Device : Address is address of Slave I2C. not local (slave memory) address, because it’s possible to have many I2C devices connected to a single I2C bus; in addition, any of them could become master;
4. Write : or Read operation is for I2C data where Write means trasmitted outof and Read means received into;
5. It`s up to designer how to use these I2C data, it could be local (slave memory) address or data;
6. Local address must be transmitted out of the master, so it must be Write opertion, even if it’s address to read data from local slave memory
7. Read operation is only in the case to read data from a local memory slave
8. Every byte must be followed by 9^th bit for acknowledgement;
9. Every byte must be acknowledged by Master/Slave Receiver, excepted the last byte of Read operation
10. A byte is acknowledged when a master sends a clock SCK and releases the data SDA for the slave to hold the data to ZERO
11. The last byte of Read operation must NOT be acknowledged where the slave NOT to hold the data SDA to signify the master to end Read operation by STOP;
12. Data change only during SCK low, the exception is Start/Stop where data change during SCK high

Data are captured @posedge SCK

States change @ negedge SCK

Change @ negedge, capture @ posedge

02/19/2003