Using HCPL-3700 from Agilent Technology.

For the mode of Input Clamp Voltage, we have

Vihc2 = 6.7 v

|Iin| = 10 mA

we have

Vr = Vpk - Vihc2 = 240*1.414 - 6.7 = 332.7 v

So

Rx = Vr / |Iin| = 332.7 / 10 = 33.3 K

R_{x/2} = 16.7 K

Use R_{x/2} = 18.7 K, 1%, so

P_{x/2} = (Vr/2)^{2 }/ R_{x/2} = 1.5w

Choose

**R _{x/2} = 18.7 K,1%, 1.5 w**

Question:

Div2 is a flip-flop to divide 120 Hz for 60 Hz

RL is not required ???

Using HCNR-0201 from Agilent Technology.

Data sheet gives I_{F }= 1 ~ 20 mA, choose I_{F} = 2 mA, we have

R_{3} = (V_{CC}
- V_{F})/I_{F} = 5/2 = 2.5 K

Data sheet gives

I_{PD1} = K_{1} * I_{F} = 0.5 * 2 = 1 mA

so

R_{1} = V_{IN} / I_{PD1} = 5/1 = 5 K

as V_{IN} is an analog signal out of a 5-v DAC (Digital Analog Converter)

Data sheet gives

I_{PD2} = K_{3} * I_{PD1} = 1 * 1 = 1 mA

so

R_{2} = V_{CC} / I_{PD2} = 5/1 = 5 K

C_{1} is for C_{1}R_{1} to meet F_{max}

C_{2} is for C_{2}R_{2} to meet F_{max}