Experiences
Communist Re-Education under harsh Control by Communist Police per
failure in failure of Runaway from Evil Communist VN on 7th June1980 till
31st 1984
07 June 1980 to 31 Aug 1984 Hard Labor
5years doing hard labor on Rice field in Evil Communist VN vs 6 yers in hard working on PhD in Australia
As digger in making canal irrigation for rice field
As buffalo in plowing rice field
The socument below say My Re-education per my Runaway to Oversea
started on June 7th 1980 and signed by Nguyen Van Ut Deputy Police
Chief Of province Minh Hai on 31st Aug 1984 to release to home home at
2 Dong Tam, phuong 3 Q Tan Binh Ho Cho Minh City
Sr SW Developer
[embeded ARM Linux for TI AM3358]
Mission MicrowaveContract May
2016 - Jun 2016
Santa FE Spring, CA
Suddendly Ended after Stroke on Free Wway 105 at speed 60+ mph
from LAX a/p to workplace at Mission Microwave Santa FE Spring Even
just a very short time but I could complete the target product fully
operational running on Linux Using TI ARMLinux SDK adap uboot to custom
HW based on BeagleBone open HW circuit partition SD card into 3
partition 1) FAT for u-boot +Kernel + Device tree 2] Ext4 for Rd Only
Root File SystemRFS[3 Ext4 for RFS bak up TFTP used to update new
u-boot and also load kernel + Devive tree for debugging testing NFS
used for testing RFS RFS was build from scratch using Build Root 2015
with SSH for access to target from host PC using PuTTY on PC Samba3 for
file update using Window Explorer on PC Apache to configure target from
browser on host PC to WebSrvr on target I have verified these features
fully operational on BeagleBone brd I developped a special IP Sever run
on target after boot And an app on PC named IP_Detector on host to
find out IP addr set by DHCP to target for network connection But
unfortunately unable fully to implement on target However the Root File
System passed to my SW partner included them all just used it due to my
sudden
stoke stoped me in guiding him how to use them so on the target
product Man propose God dispose though!!Suddendly
Ended after Stroke on Free Wway 105 at speed 60+ mph from LAX a/p to
workplace at Mission Microwave Santa FE Spring Even just a very short
time but I could complete the target product fully operational running
on Linux Using TI ARMLinux SDK adap uboot to custom HW based on
BeagleBone open HW circuit partition SD card into 3 partition 1) FAT
for u-boot +Kernel + Device tree 2] Ext4 for Rd Only Root File
SystemRFS[3 Ext4 for RFS back up TFTP used to update new u-boot and
also
load kernel + Devive tree for debugging testing NFS used for testing
RFS RFS was build from scratch using Build Root 2015 with Samba for
Window FileAcces via Window Explorer ; SSH for
access to target from host PC using PuTTY on PC Samba3 for file update
using Window Explorer on PC Apache to configure target from browser on
host PC to WebSrvr on target I have verified these features fully
operational on BeagleBone brd I developped a special IP Sever run on
target after boot And an app on PC named IP_Detector on host to find
out IP addr set by DHCP to target for network connection The
whole Root File System on the target included them all just configured
and run them But
unfortunately unable fully to demo these features on target due to my
sudden
stoke stoped me in doing so Man propose God dispose though!!
Sr R&D Eng FPGA Verilog/ embedded SW
bare-metal system using Dual Core TI OMAP-L138=ARM9+DSP
Venture Design Service Contract Mar
2013 - Mar 2015
Santa Rosa, California,
United States
Santa Rosa, California, United States Upgrade Xilinx
Virtex FPGA using Verilog with DSP Core for better product quality for
sustaining revenue As a embedded SW Developer using C from TI BSP for
bootup ARM core and DSP core including USB stack in new product using
using TI OMAP-L138 with dual-core ARM9 AM1808 and DSP C6748 with TI
Code-Composer Studio v.5 As PC SW Developer using C#with LibUsb DotNet
for high speed USB at 12 Mbps 100x faster than 115Kbps in DCDC serial
comm mode in flashing new image from PC onto target via USB
cableUpgrade Xilinx Virtex FPGA using Verilog with DSP Core for better
product quality for sustaining revenue As a embedded SW Developer using
C from TI BSP for bootup ARM core and DSP core including USB stack in
new product using using TI OMAP-L138 with dual-core ARM9 AM1808 and DSP
C6748 with TI Code-Composer Studio v.5 As PC SW Developer using C#with
LibUsb DotNet for high speed USB at 12 Mbps 100x faster than 115Kbps in
DCDC serial comm mode in flashing new image from PC onto target via USB
cable Skills: PID Controller for Oscillator DisciplineSkills: PID
Controller for Oscillator Discipline
Sr R&D Eng FPGA Verilog embeded
Linux x86 [Kontron ]+PowerPC MPC 8013/8272]
SYMMETRICOM, LTD. Full-time Feb 2002 -
Feb 2013
Santa Rosa,
California, United States
Handle all technical challenges in theory or in practice at Symm
including its division in San Jose and Boulder Colorado beyond my duty
and belong to my boss's duty like mentoring 2 Sr HW engs to use Verilog
instead of discrete logic gates; solved all tek problems regardless
near or far away with biz trip Upgrade all timing products with new HW
board/Xilinx FPGA using Verilog for better quality and better profit
with new part better quality ang better price Protype Board Bring Up in
extreme short time owing to my product architect assuming the prototype
not working and some fetures in this scenario added into architect I
have to admit I could not do that well without this architect built for
debugging As a member in new SW Development team on embedded x86 Linux
for time Server using x86 Kontron SBC[Single Board Computer)
responsible in FPGA dev and configuring Linux Kernel to Symm brd and
attempted bare minimum Root File System with only BusyBox and Bash Life
span of X86 is limited to 5 years far below customer expect of 10+yrs
As member in new SW Development Team of bedded PowerPC Linux for Time
Server using PowerPC MPC8013 responsible in adapting u-boot to new
Symmetricom custom HW, FPGA dev and configuring Linux Kernel based on
our new HW and attempt with bare minimum Root Filewith only BusyBox and
Bash bring up new Protype and testing Embed Linux File System over
network using TFTP for kernel new u-boot update and NFS for Root File
System testing One of key contributor to the first Symmetricom Grand
Master PTP responsible in FPGA design of Time Stamp based on my solid
knowledge on Ethernet Frame as one of Developer in Team making the
Grand Master PTP v01 in both FPGA and SW and sucessfully updating to
PTPv2 at both Santa Rosa/SanJose/Boulder Colorado Symmetricom in both
FPGA and embedded SW in Oscilator Disclipline Using my solid knowledge
on PID Control and on TCIP Ethernet Frame with PTP packetHandle all
technical challenges in theory or in practice at Symm including its
division in San Jose and Boulder Colorado beyond my duty and belong to
my boss's duty like mentoring Sr HW eng to use Verilog instead of
discrete logic gates; solved all tek problems regardless near or far
away with biz trip Upgrade all timing products with new HW board/Xilinx
FPGA using Verilog for better quality and better profit with new part
better quality ang better price Protype Board Bring Up in extreme short
time owing to my product architect assuming the prototype not working
and some fetures in this scenario added into architect I have to admit
I could not do that well without this architect built for debugging As
a member in new SW Development team on embedded x86 Linux for time
Server using x86 Kontron SBC[Single Board Computer) responsible in FPGA
dev and configuring Linux Kernel to Symm brd and attempted bare minimum
Root File System with only BusyBox and Bash Life span of X86 is limited
to 5 years far below customer expect of 10+yrs As member in new SW
Development Team of bedded PowerPC Linux for Time Server using PowerPC
MPC8013 responsible in adapting u-boot to new Symmetricom custom HW,
FPGA dev and configuring Linux Kernel based on our new HW and attempt
with bare minimum Root Filewith only BusyBox and Bash bring up new
Protype and testing Embed Linux File System over network using TFTP for
kernel new u-boot update and NFS for Root File System testing One of
key contributor to the first Symmetricom Grand Master PTP responsible
in FPGA design of Time Stamp based on my solid knowledge on Ethernet
Frame as one of Developer in Team making the Grand Master PTP v01 in
both FPGA and SW and sucessfully updating to PTPv2 at both Santa
Rosa/SanJose/Boulder Colorado Symmetricom in both FPGA and embedded SW
in Oscilator Disclipline Using my solid knowledge on PID Control and on
TCIP Ethernet Frame with PTP packet Skills: PID Controller for
Oscillator Discipline Embedded Software C (Programming
Language)bare metal realtime system embedded Linux Schematic
CaptureSkills: PID Controller for Oscillator Discipline Embedded
Software C (Programming Language)bare metal realtime system embedded
Linux Schematic Capture
Another my big contribution to Symmetricom was I manage production team
to programming product more covenience and professional way
No body was aware of Endianess to guide product team using programmer per product text image
All product were not operational after programmed and
TrueTime/Symetricom had a get-around by send tothem a programmed flash
made by debugger tool
They just simply put the programmed flash in the programmer for duplicating/cloning to brand new flash
I was horrified to learn such clumsy production way so I guide the team
how to use product image in text send via email and all product were
operational upon getting from them
R&DEngr [HW FPGA Verilog &Low-Level SW Driver for
MicroController Motorola 68331
Next Level Communication start up Full-time Aug 1997 - Nov
2001
Rohnert Park, California, United States
I didn't have enough patience to wait for SW Enineer to bring up my HW prototype
So my main job was HW but SW job was bonus for NLC, I was a generous Engineer
So I self trained myself to bringup my HW prototype
Even as a HW engr But I was still able to fix big SW bug in Main Phone Operating SW system as detailed below
I make a boot code based on HW component RAM in particular
I also developed program&procedure to test and programing product binary image onto eeprom for production dept
In particular to use programer properly with product image in txt Srecrord with cottect Endianess
My boot code had ZERO waitstate
But SW Engineer used boot code from a purchased SW package for
Motorola 68331 which used SOME waitstate
His job scrued up the Main Phone operating system using 1-sec
ISR(Intterupt Sevice Routine) to monitor calling time on phone
billing purpose
I was asked to fixed my HW bcz the ISR could not run some code at bottom of ISR for time phone billingpurpose
I verified the problem with my code but it ran smoothly all the way to the end
I was forced to fix my HW but I didn't agree and showed my test
The whole NLC was in panic on the problematic Main Phone operating system
So I decide to look at the main System code and found the diff was NON ZERO waistate
that's why ISR run slower could not complete in 1 sec and some code at boottom not executed
I change to ZERO waista state
The Main Phone operating system worked properly
I was so mad and came to my manager's office and told him IDIOTS
Has any PC ever been opened for fix when SW ill behave
Therefore my name was on the layoff list
But no more new products released
since my depart and Rohnert Park office was closed down per poor pergformance 3 year after my layoff
I was the most agressive Engr with frequent new product released about twice yearly
My main job were CircuitDesign / Xilinx & Altera FPGA design using Verilog to
develop SONET frame for new digital communication system and Voice over
IP using micro controller 68331 bring up prototype board using C with
boot code and HW driver for MC68331 Develop SW in C used in production
test/prgramming image onto EEPROM memory and QA Product
testCircuitDesign / Xilinx & Altera FPGA design using Verilog to
develop SONET frame for new digital communication system and Voice over
IP using micro controller 68331 bring up prototype board using C with
boot code and HW driver for MC68331 Develop SW in C used in production
test/prgramming image onto EEPROM memory and QA Product test Skills:
embedded C for MC68331[ bootcode and EEPROM programming and driver
Schematic CaptureSkills: embedded C for MC68331[ bootcode and EEPROM
programming and driver Schematic Capture
UniversityTutor
University Technology Sydney Part-time Part-time Feb 1994 - Aug 1997
Sydney, New South Wales,
AustraliaSydney, New South Wales,
Australia
Control Lab Assist Final year EE students including Master students in
Fuzzy Logic field and praticing Engineer in Control Lab to design both
analog/digital and controller for small scale dynamic systems used in
Co0ntrol Lab like Ball Beam, Ball Plate, Off shore Crane, Over-Head
Crane, Inverted Pendulum, Couple Drive 1] Do System
identification=="Use Physic Theory to find Mathematical Model of the
target system 2] Do System Validation on the Mathematical model 3]
Design Analog Controller using Op-Amp 4] Design Digital Controller
using Pascal language run on PC with50mSec DOS system interrupt as
sampling time of 20mSec 5] Help student setup PC Env to get them
familar with the procedure at early stage 6] Solve their problem in
later stage The time session in evening for praticing Engineer to
attend occasionally I stayed with them till midnight to work out on
their problems There were a lot of fun then This job build up my real
experience in control pratice and in especially in Oscilattor
Discipline Mentoring Graduation Project Graduation Thesis:: Consulting graduating
student in their chalenging/advanced project for Bachelor of Electrical
Engineering graduation project in DSP/Fuzzy Logic ControlControl Lab
Assist Final year EE students including Master students in Fuzzy Logic
field and praticing Engineer in Control Lab to design both
analog/digital and controller for small scale dynamic systems used in
Co0ntrol Lab like Ball Beam, Ball Plate, Off shore Crane, Over-Head
Crane, Inverted Pendulum, Couple Drive 1] Do System
identification=="Use Physic Theory to find Mathematical Model of the
target system 2] Do System Validation on the Mathematical model 3]
Design Analog Controller using Op-Amp 4] Design Digital Controller
using Pascal language run on PC with50mSec DOS system interrupt as
sampling time of 20mSec 5] Help student setup PC Env to get them
familar with the procedure at early stage 6] Solve their problem in
later stage The time session in evening for praticing Engineer to
attend occasionally I stayed with them till midnight to work out on
their problems There were a lot of fun then This job build up my real
experience in control pratice and in especially in Oscilattor
Discipline Mentoring Graduation Project Thesis:: Consulting graduating
student in their chalenging/advanced project for Bachelor of Electrical
Engineering graduation project in DSP/Fuzzy Logic Control Skills:
Computational Physics PIDControl State space Control Analog
Control using OpAmpSkills: Computational Physics PIDControl State
space Control Analog Control using OpAmp
AI ResearcherAI Researcher
University of Technology
Sydney Contract Feb 1995 - Sep 1995
New South Wales, AustraliaSydney, New South Wales,
Australia
Basically AI process employs math optimization to set link-weight in
neu-net to get expected output per training data Originally Steepest
Descent Optization Method was used as math optimization in AI In my AI
R&D at UTS per contract with Medical Center in providing training
data from diabetic patient with expected output result as diabetic true
value AI neu-net to be found so they apply another patient data to find
out potential diabetic patient Unfortunately my AI neu-net gave
incorrect result while another R&D party from some somewhere else
was correct The reason of Its failure has been hanging over my head
since then Recently I probably got the answer Nothing can be done on
neu-net except initial random value of link-weight So both parties used
more/less the same neu-net with link-weight initially set with random
value They could used more number of neuron than I used but probably
not much higher due to limit of PCHW then with486 +Math Coprocessor and
few hundreds MB RAM Per my experience in setup/hold time with FPGA I
did help to solve intermittent performance for a Linux Contract at
Symmetricom Colorado and I just use a dump short for loop to slow down
his code in write operations and the problem went away I used new
advanced Optimization Method namely Conjugate Gadient Method in my AI
R&D at UTS the other parry might use method originally employed in
AI The original method used fixed learning rate to minimize error The
new advanced method uses varying learning rate to minimize error and
also maximize error reduction change so it get minimum error and
minimum process time as well==> at 20x time faster than the original
Optimization Probably I got wrong link-weight due to very fast process
violating sretup/hold time where the value of link-weight are not
stable during time being updated I found a dilemma in my AI experience
at UTS Fast process give wrong result Slow process responds too late
for timing event That's why AI chip could be the solutionBasically AI
process employs math optimization to set link-weight in neu-net to get
expected output per training data Originally Steepest Descent
Optization Method was used as math optimization in AI In my AI R&D
at UTS per contract with Medical Center in providing training data from
diabetic patient with expected output result as diabetic true value AI
neu-net to be found so they apply another patient data to find out
potential diabetic patient Unfortunately my AI neu-net gave incorrect
result while another R&D party from some somewhere else was correct
The reason of Its failure has been hanging over my head since then
Recently I probably got the answer Nothing can be done on neu-net
except initial random value of link-weight So both parties used
more/less the same neu-net with link-weight initially set with random
value They could used more number of neuron than I used but probably
not much higher due to limit of PCHW then with486 +Math Coprocessor and
few hundreds MB RAM Per my experience in setup/hold time with FPGA I
did help to solve intermittent performance for a Linux Contract at
Symmetricom Colorado and I just use a dump short for loop to slow down
his code in write operations and the problem went away I used new
advanced Optimization Method namely Conjugate Gadient Method in my AI
R&D at UTS the other parry might use method originally employed in
AI The original method used fixed learning rate to minimize error The
new advanced method uses varying learning rate to minimize error and
also maximize error reduction change so it get minimum error and
minimum process time as well==> at 20x time faster than the original
Optimization Probably I got wrong link-weight due to very fast process
violating sretup/hold time where the value of link-weight are not
stable during time being updated I found a dilemma in my AI experience
at UTS Fast process give wrong result Slow process responds too late
for timing event That's why AI chip could be the solution Skills:
Optimazation Method in MatLab Artificial Intelligence (AI)