Experiences
Communist Re-Education under harsh Control by Communist Police per
failure in Runaway from Evil Communist VN on 7th June1980 till
31st 1984
07 June 1980 to 31 Aug 1984 Hard Labor
5years doing hard labor on Rice field in Evil Communist VN vs 6 yers in hard working on PhD in Australia
As digger in making canal irrigation for rice field
As buffalo in plowing rice field
The socument below say My Re-education per my Runaway to Oversea
started on June 7th 1980 and signed by Nguyen Van Ut Deputy Police
Chief Of province Minh Hai on 31st Aug 1984 to release to home home at
2 Dong Tam, phuong 3 Q Tan Binh Ho Cho Minh City
AI ResearcherAI Researcher
University of Technology
Sydney Contract Feb 1995 - Sep 1995
New South Wales, AustraliaSydney, New South Wales,
Australia
I
was given training data on diabete from NSW Medical Center and I solely
resposible in using matlab language using Onumerical Optimal methods
Desent gradient and onjugate gradient
Basically AI process employs math optimization to set link-weight in
neu-net to get expected output per training data Originally Steepest
Descent Optization Method was used as math optimization in AI In my AI
R&D at UTS per contract with Medical Center in providing training
data from diabetic patient with expected output result as diabetic true
value AI neu-net to be found so they apply another patient data to find
out potential diabetic patient
I used both simple Descent Gradient and advnced methods Method namely Conjugate Gadient Method in my AI
R&D at UTS
employed in
AI The original method used fixed learning rate to minimize error The
new advanced method uses varying learning rate to minimize error and
also maximize error reduction change so it get minimum error and
minimum process time as well==> at 20x time faster than the simple
Optimization
Basically AI
process employs math optimization to set link-weight in neu-net to get
expected output per training data Originally Steepest Descent
Optization Method was used as math optimization in AI In my AI R&D
at UTS per contract with Medical Center in providing training data from
diabetic patient with expected output result as diabetic true value AI
neu-net to be found potential diabetic patient
time as well==> advanced method bothoptimize both error value and
gradient direction So athe advance 20x time faster than the
simple
R&DEngr [HW FPGA Verilog &Low-Level SW Driver for
MicroController Motorola 68331
Next Level Communication start up Full-time Aug 1997 - Nov
2001
Rohnert Park, California, United States
R&D Engineer[HW/FPGA/Lowlelvel SW for Motorola PwerPC PowerQikk and Micro
Controller MCU 68331]
My contributions
1. 3 new products as basis of other new product tin 3 years
My VN college mate name [Lac] had close relationship with CEO
cofounder
It has hard to find new engineer in USW due to dot com boom
So he ask NLC to offer HB1 visa for me to come from Australia for
this job
in the new of only 3 including Lac and another VN eng also from
AUS before me 2 years he was from the same College in VN but 1 yr below me
Time was very critical no delay allowed absolutely
In every meeting of NPLI [ New Product Imitative] Lac took all troublesome
projects and asked me to completed by myself from schematic bring up the board
bring up with low-level driver including EEPROM programming for Motorola micro
controller MCI and Power PC Power Qikk
At NLC I was the only engineer had no prj canceled as All my prj was complete too quick so when the
Board Director learn my it was done so no cancellation at all I also managed to
help Production to do EEPROM programming of product binary image FW and Test as
well One of my contribution was to include FPGA image along with product SW image
and develop low level SW to configure and bringup FPGA and thru this I learn
the diff between Intel and Motorola. This experience was the basis of my
contribution at Symmetricom later on
Within a short time of 3 yrs at NLC with 3 new product basis for
other new product at the time
I completed all my duties quick and had time to help others in same group or in
diff group
SW team at NLS asked their HW partner copy my FPGA way to make
their SW task a lot easier fully under SW control
I was laid off per a
strong argument with an Indian migrant Director as he asked to fix the HW on Sw
problem
when SW cannot finish 1 millisecond IZSR[interrupt Service
Routine in iming the phone call for Bill charge
I developed my own test and verify it could complete the whole
ISR
But he still asking me to fix my HW
I asked him if he fix his PC if it has SW problem . He was mad
and keep asking me to fix the HW
So I asked for the buggy S code
and ound the bug
In all my prj and provide my low-level code to my SW partner
But the SW eng asked NLC to purchase Motorola BSP B dPackage Support] along with new boot code with different Wait State
[WS]to mine
In the old day memory was slow so MCU[Micro Controller] includes
Wait State WS] for propermemory acess
Per specs of onbrd memory I set WS=1 in my boot code so the ISR could completeproperly the whole
ISR and WS>1 in boot code in purchased boot code in Motorola BSP [ Brd upport Package] so it take
longer to finish ISR so m-S ISR could not run properlysome of the code near end
of ISr were not executed
I asked for the boot code in Motorola BSP and found WS>1 so
the 1-mSec ISR could not run in 1 millisec
I change it to 1 and it worked prefectly
I came to his technical support who asked my to fix the HW and told him IDIOT
That's why I was in the following layoff list
Then no more new product in 2 years since my departure anf the
biz was closed down by Motorola after acquisition per per its worse performace than other's acquisition
Later on the Dir had an job interview at Symmetricomas we both
at NLC
I was asked for his
performance My reply was the story above
with no other extra comment so his interview was cancelled
I believe Iwas proper in this event as he had bad mannage ment
skill and no logical thinking
I completed my PhDEE in 2
years after my Master at UTS it was pretty short as it was an quite advanced
upgrade of my Master My PhD superviosor
was unable to follow my thesis even with biweekly recover meeting progress
report and seminar every qarterly So he hesitated to submit to an external examiner outside of
UTS
Therefore I left for this
startup job in to force his sub mission Otherwise I may find way to
submit here in USA It's fair in doing so as the supervisor simply offered the
toppic and all the rest I solely work on my own it's with a lot of math Theorem
so the supervisor could not follow
As expected he submitand it was evaluated at high stangard wth
some critical original contributions into the field
MPC 8013/8272]
SYMMETRICOM, LTD. Full-time Feb 2002 -
Feb 2013
Main Contributions
- Solely Precise Time Protocol[PTP] with FPGA and Ocilator Dicipline in PTPv2 upgrade
- Active Team member of embeded Intel/Power PC embeded Linux
Cover Chief
Scientist duties of my direct manager handling all technical
challenges both in theory or in practice allover Symm at mmany
different places in San Jose HQ and Boulder Colorado Beverly
MAssachusette Division ; beyond my duty ike mentoring 2 Sr HW engs to use Verilog
instead of discrete logic gates; solved all tek problems regardless
near or far away with biz trip Upgrade all timing products with new HW
board/Xilinx FPGA using Verilog for better quality and better profit
with new part better quality ang better price Protype Board Bring Up in
extreme short time owing to my product architect assuming the prototype
not working and some fetures in this scenario added into architect I
have to admit I could not do that well without this architect built for
debugging As a member in new SW Development team on embedded x86 Linux
for time Server using x86 Kontron SBC[Single Board Computer)
responsible in FPGA dev and configuring Linux Kernel to Symm brd and
attempted bare minimum Root File System with only BusyBox and Bash Life
span of X86 is limited to 5 years far below customer expect of 10+yrs
As member in new SW Development Team of bedded PowerPC Linux for Time
Server using PowerPC MPC8013 responsible in adapting u-boot to new
Symmetricom custom HW, FPGA dev and configuring Linux Kernel based on
our new HW and attempt with bare minimum Root Filewith only BusyBox and
Bash bring up new Protype and testing Embed Linux File System over
network using TFTP for kernel new u-boot update and NFS for Root File
System testing One of key contributor to the first Symmetricom Grand
Master PTP responsible in FPGA design of Time Stamp based on my solid
knowledge on Ethernet Frame as one of Developer in Team making the
Grand Master PTP v01 in both FPGA and SW and sucessfully updating to
PTPv2 at both Santa Rosa/SanJose/Boulder Colorado Symmetricom in both
FPGA and embedded SW in Oscilator Disclipline Using my solid knowledge
on PID Control and on TCIP Ethernet Frame with PTP packetHandle all
technical challenges in theory or in practice at Symm including its
division in San Jose and Boulder Colorado beyond my duty and belong to
my boss's duty like mentoring Sr HW eng to use Verilog instead of
discrete logic gates coaching another Sr Eng to complete his project; solved all tek problems regardless near or far
away with biz trip Upgrade all timing products with new HW board/Xilinx
FPGA using Verilog for better quality and better profit with new part
better quality ang better price Protype Board Bring Up in extreme short
time owing to my product architect assuming the prototype not working
and some fetures in this scenario added into architect I have to admit
I could not do that well without this architect built for debugging As
a member in new SW Development team on embedded x86 Linux for time
Server using x86 Kontron SBC[Single Board Computer) responsible in FPGA
dev and configuring Linux Kernel to Symm brd and attempted bare minimum
Root File System with only BusyBox and Bash Life span of X86 is limited
to 5 years far below customer expect of 10+yrs As member in new SW
Development Team of bedded PowerPC Linux for Time Server using PowerPC
MPC8013 responsible in adapting u-boot to new Symmetricom custom HW,
FPGA dev and configuring Linux Kernel based on our new HW and attempt
with bare minimum Root Filewith only BusyBox and Bash bring up new
Protype and testing Embed Linux File System over network using TFTP for
kernel new u-boot update and NFS for Root File System testing One of
key contributor to the first Symmetricom Grand Master PTP responsible
in FPGA design of Time Stamp based on my solid knowledge on Ethernet
Frame as one of Developer in Team making the Grand Master PTP v01 in
both FPGA and SW and sucessfully updating to PTPv2 at both Santa
Rosa/SanJose HQ/Boulder Colorado SymmetricomDivision in both FPGA and embedded SW
in Oscilator Disclipline Using my solid knowledge on PID Control and on
TCIP Ethernet Frame with PTP packet Skills: PID Controller for
Oscillator Discipline Embedded Software C (Programming
Language)bare metal realtime system embedded Linux Schematic
CaptureSkills: PID Controller for Oscillator Discipline Embedded
Software C (Programming Language)bare metal realtime system
embedded
Linux Schematic Capture
Another my big contribution to Symmetricom was I manage production team
to programming product more covenience and professional way
to guide product team using programmer with product ninary image in text file thru email
All product were not operational after programmed and
TrueTime/Symetricom had a get-around by sending a programmed flash
made by debugger tool
They just simply put the programmed flash in the programmer for cloning to new blankflash
I was horrified to learn such clumsy un profressional production way so I guide the team
how to use product image in text send via email and all product were
operational
Sr R &D Engineer[HW/FPGA/Embeded Linux Intel PowerPC
Brd Schematicand Brd brinp up with Lowlel SW driver
My contributions were:
1. embeded Linux Intel Power PowerPC
2. FPGA design with Verilog in place of discrete logic design gate
3. PTP Master Clock FPGA Oscilator Discipline
3. I complete my task qik and had spare time to
help other to complete their task or solve all tek problem for Customer CARE GROUP
4. Mentoring a Sr HW engineer to update his FPGA
from discrete logic gate to Verlilog after a 1-month Verilogclass at Sanjose c
He was excellent in his logic gate So I coach hime how to map his logic gate
design to Verlog design
Also oaching another Sr HW Engineer to complete his prj
5. Proper flash programming at manufacture
At manufacture, Flash prograamin was handle improperly with programming machine
with proguct image file product faile to worked with new programed flash
a onbrd flash was programmed under
debuggerusing programming On-brd was program under debugger
Then it was takken off the bord with unsoldering and sent to manufacture for
cloning
IUnder my close supervision the flash programming were done properly on
programmin machine with product image
Then no need flash cloning
6. Indepedently prj failed thr 5 managers across
different division : Santa Rosa Boulder
Colorado
The secret was I was dood at both SW/HW while they know only one
I was hired as Sr R&D Eng at the right time with myonlew few bugs left in my
bank acct with house wife and 3 kids ade 3 and 2 at a rental appart ment
My manager was a PhD Hief Scientitst[CS]
But I'm suspicious his PhD as his capality was too weak for a
PhD qualification
During 11 year I had to cover his CS duties without any
promotion at all
while I double salary of the whole dept I was responsile about
few dozen of skilled worker and few engineers
At Symm in all [New Product Initiative]
meetings all critical decision made by myself CSci just simply repeat all my statementsme
statement without any extra new
Whenever any problem arise at any Division in HQ San Jose or
Division in Colorado or Beverly Massachuset he arrange a biz trip for me going there to solve
it
I had to handle all problemunder his responsible CS-duties
I had no promotion since my job start in 2001 till 2006 when new
Director, say name D, hired He recognize
my capability found CS misleading only
fewmonths into his job while no one at Symm could find the misleading chracter
of CS nfor years from True Time to Symm after acquisition
One day the new Dir came into to my office cubicle and complained his failure in promoting me
I knew right away the CS stole and claimed all my achievements
Later
on I asked VP ENgineering to let me work by solely and indepently
myself in a new qik response group directly working with
custiomer via biz trip
But the VP did not approve
After the VP left the CS offered apology to me when he asked the VP
nreject my
idea
I know right away
The CS hardly kept his job with out my support both in practice
and in theory
He was very excellent in appeasing others to hide his
incompetence
I found his LI profile with PhD EE at Ilinois 1982-1986
I managed to contact Ilinois Alumni and got confirm his name not
on the list PhD in period 1982-1986
I emailed him the confirm and he changed to PhD EE Michigan
1982-1988
It's interesting when a
guy just simply claim PhD and got CS job
In VN a fake certificate of degree was used but in USA no
need of fake certificate just a fake claimWhat USA PhD !!!
Now Ichallenge him to put his PhD thesis on his profilr on L I
as I did
Wehe he was asked to host a upgrade of PTP from ver 1 to ver 2
He created a group of contractor
But he failed to do the task and blame his simulation showed the
model was exploded that is he's not responsible for his failure
But a Symm SW eng, not contractor in the team came to ask my help
I gave him my object code to use in his Sw and the upgrade done
The root cause was the CS had no idea on Oscilator discipline
even I found a lof of books about PID on his desk
Bsed on the sucees on PTP master clock the CS applied for PTP
chairman of PTP commitee
my cubicle was next to his so I can hear all his nonsense on PTP
in ever phome meeting wit the commitee
When a PTP problem arise at Symmetricom
The problem owner,say name P asked for his help but he could not
solve in quite long time so P lost his patience and asked my help I solved his
problem within minutes
wondering how he gets ashamed on his il behavior as a misleading manager earn his living on other's burden
He suposed to be a politician instead of professional
Sr R&D Eng FPGA Verilog/ embedded SW
bare-metal system using Dual Core TI OMAP-L138=ARM9+DSP
Venture Design Service Contract Mar
2013 - Mar 2015
Santa Rosa, California,
United States
Santa Rosa, California, United States Upgrade Xilinx
Virtex FPGA using Verilog with DSP Core for better product quality for
sustaining revenue As a embedded SW Developer using C from TI BSP for
bootup ARM core and DSP core including USB stack in new product using
using TI OMAP-L138 with dual-core ARM9 AM1808 and DSP C6748 with TI
Code-Composer Studio v.5 As PC SW Developer using C#with LibUsb DotNet
for high speed USB at 12 Mbps 100x faster than 115Kbps in DCDC serial
comm mode in flashing new image from PC onto target via USB
cableUpgrade Xilinx Virtex FPGA using Verilog with DSP Core for better
product quality for sustaining revenue As a embedded SW Developer using
C from TI BSP for bootup ARM core and DSP core including USB stack in
new product using using TI OMAP-L138 with dual-core ARM9 AM1808 and DSP
C6748 with TI Code-Composer Studio v.5 As PC SW Developer using C#with
LibUsb DotNet for high speed USB at 12 Mbps 100x faster than 115Kbps in
DCDC serial comm mode in flashing new image from PC onto target via USB
cable Skills: PID Controller for Oscillator DisciplineSkills: PID
Controller for Oscillator Discipline
3. Venture Design Service VD Rosa
California
03-2011~2015
FPGA Embeded SW Contractor
Contribution: true USB speed high speed 12 Mbps not serial RSB
CDC speed max at 1Mbps
Zgraph in C#
I had a phone call for job interview
I was persuaeded to get a contractor job for a quick offer and
with a promise as a permanent job while I already had a permanent job interview
at National Instrument in Codding town plaza
laid off due bad manaer in seeking perfect product
and didn't release the product But he insisted he'd got bbad
reputation with imperfect product
I convince him to release product
as I had remote upgrade builtin o product for quick flash
programminf via True USAB at 12 Mbps and product could easiyupdatedat custner
site with new FW with bug fx or neew feature
No customer for a late release
VDS was shut down few months after my lay off
This was the very first time my project was cancelled due cincompetitive
manager with cray biz practice
His failure was his expect was well above his ability
4. Mission Microwave Santa FE Spring California
05-2016~09-20162015
Ihad a phone call for job inter view
I was able to bring up embed Linux with full network feature within 1 week at
job start
I was laid off after 1 month with my stroke
in dving on ee way at hi speed from LA airport to Mission
mirowave at AntaFe Sprind after home visi in Cotati Hiway Police was able to
stop my car with no accident and call ambulance formergency 025 not yet
recovered
I didn't have enough patience to wait for SW Enineer to bring up my HW prototype
So my main job was HW but SW job was bonus for NLC, I was a generous Engineer
So I self trained myself to bringup my HW prototype
Even as a HW engr But I was still able to fix big SW bug in Main Phone Operating SW system as detailed below
I make a boot code based on HW component RAM in particular
I also developed program&procedure to test and programing product binary image onto eeprom for production dept
In particular to use programer properly with product image in txt Srecrord with cottect Endianess
My boot code had ZERO waitstate
But SW Engineer used boot code from a purchased SW package for
Motorola 68331 which used SOME waitstate
His job scrued up the Main Phone operating system using 1-sec
ISR(Intterupt Sevice Routine) to monitor calling time on phone
billing purpose
I was asked to fixed my HW bcz the ISR could not run some code at bottom of ISR for time phone billingpurpose
I verified the problem with my code but it ran smoothly all the way to the end
I was forced to fix my HW but I didn't agree and showed my test
The whole NLC was in panic on the problematic Main Phone operating system
So I decide to look at the main System code and found the diff was NON ZERO waistate
that's why ISR run slower could not complete in 1 sec and some code at boottom not executed
I change to ZERO waista state
The Main Phone operating system worked properly
I was so mad and came to my manager's office and told him IDIOTS
Has any PC ever been opened for fix when SW ill behave
Therefore my name was on the layoff list
But no more new products released
since my depart and Rohnert Park office was closed down per poor pergformance 3 year after my layoff
I was the most agressive Engr with frequent new product released about twice yearly
My main job were CircuitDesign / Xilinx & Altera FPGA design using Verilog to
develop SONET frame for new digital communication system and Voice over
IP using micro controller 68331 bring up prototype board using C with
boot code and HW driver for MC68331 Develop SW in C used in production
test/prgramming image onto EEPROM memory and QA Product
testCircuitDesign / Xilinx & Altera FPGA design using Verilog to
develop SONET frame for new digital communication system and Voice over
IP using micro controller 68331 bring up prototype board using C with
boot code and HW driver for MC68331 Develop SW in C used in production
test/prgramming image onto EEPROM memory and QA Product test Skills:
embedded C for MC68331[ bootcode and EEPROM programming and driver
Schematic CaptureSkills: embedded C for MC68331[ bootcode and EEPROM
programming and driver Schematic Capture
UniversityTutor
University Technology Sydney Part-time Part-time Feb 1994 - Aug 1997
Sydney, New South Wales,
AustraliaSydney, New South Wales,
Australia
Control Lab Assist Final year EE students including Master students in
Fuzzy Logic field and praticing Engineer in Control Lab to design both
analog/digital and controller for small scale dynamic systems used in
Co0ntrol Lab like Ball Beam, Ball Plate, Off shore Crane, Over-Head
Crane, Inverted Pendulum, Couple Drive 1] Do System
identification=="Use Physic Theory to find Mathematical Model of the
target system 2] Do System Validation on the Mathematical model 3]
Design Analog Controller using Op-Amp 4] Design Digital Controller
using Pascal language run on PC with50mSec DOS system interrupt as
sampling time of 20mSec 5] Help student setup PC Env to get them
familar with the procedure at early stage 6] Solve their problem in
later stage The time session in evening for praticing Engineer to
attend occasionally I stayed with them till midnight to work out on
their problems There were a lot of fun then This job build up my real
experience in control pratice and in especially in Oscilattor
Discipline Mentoring Graduation Project Graduation Thesis:: Consulting graduating
student in their chalenging/advanced project for Bachelor of Electrical
Engineering graduation project in DSP/Fuzzy Logic ControlControl Lab
Assist Final year EE students including Master students in Fuzzy Logic
field and praticing Engineer in Control Lab to design both
analog/digital and controller for small scale dynamic systems used in
Co0ntrol Lab like Ball Beam, Ball Plate, Off shore Crane, Over-Head
Crane, Inverted Pendulum, Couple Drive 1] Do System
identification=="Use Physic Theory to find Mathematical Model of the
target system 2] Do System Validation on the Mathematical model 3]
Design Analog Controller using Op-Amp 4] Design Digital Controller
using Pascal language run on PC with50mSec DOS system interrupt as
sampling time of 20mSec 5] Help student setup PC Env to get them
familar with the procedure at early stage 6] Solve their problem in
later stage The time session in evening for praticing Engineer to
attend occasionally I stayed with them till midnight to work out on
their problems There were a lot of fun then This job build up my real
experience in control pratice and in especially in Oscilattor
Discipline Mentoring Graduation Project Thesis:: Consulting graduating
student in their chalenging/advanced project for Bachelor of Electrical
Engineering graduation project in DSP/Fuzzy Logic Control Skills:
Computational Physics PIDControl State space Control Analog
Control using OpAmpSkills: Computational Physics PIDControl State
space Control Analog Control using OpAmp
Sr SW Developer
[embeded ARM Linux for TI AM3358]
Mission MicrowaveContract May
2016 - Jun 2016
Santa FE Spring, CA
Suddendly Ended after Stroke on Free Wway 105 at speed 60+ mph
from LAX a/p to workplace at Mission Microwave Santa FE Spring Even
just a very short time but I could complete the target product fully
operational running on Linux Using TI ARMLinux SDK adap uboot to custom
HW based on BeagleBone open HW circuit partition SD card into 3
partition 1) FAT for u-boot +Kernel + Device tree 2] Ext4 for Rd Only
Root File SystemRFS[3 Ext4 for RFS bak up TFTP used to update new
u-boot and also load kernel + Devive tree for debugging testing NFS
used for testing RFS RFS was build from scratch using Build Root 2015
with SSH for access to target from host PC using PuTTY on PC Samba3 for
file update using Window Explorer on PC Apache to configure target from
browser on host PC to WebSrvr on target I have verified these features
fully operational on BeagleBone brd I developped a special IP Sever run
on target after boot And an app on PC named IP_Detector on host to
find out IP addr set by DHCP to target for network connection But
unfortunately unable fully to implement on target However the Root File
System passed to my SW partner included them all just used it due to my
sudden
stoke stoped me in guiding him how to use them so on the target
product Man propose God dispose though!!Suddendly
Ended after Stroke on Free Wway 105 at speed 60+ mph from LAX a/p to
workplace at Mission Microwave Santa FE Spring Even just a very short
time but I could complete the target product fully operational running
on Linux Using TI ARMLinux SDK adap uboot to custom HW based on
BeagleBone open HW circuit partition SD card into 3 partition 1) FAT
for u-boot +Kernel + Device tree 2] Ext4 for Rd Only Root File
SystemRFS[3 Ext4 for RFS back up TFTP used to update new u-boot and
also
load kernel + Devive tree for debugging testing NFS used for testing
RFS RFS was build from scratch using Build Root 2015 with Samba for
Window FileAcces via Window Explorer ; SSH for
access to target from host PC using PuTTY on PC Samba3 for file update
using Window Explorer on PC Apache to configure target from browser on
host PC to WebSrvr on target I have verified these features fully
operational on BeagleBone brd I developped a special IP Sever run on
target after boot And an app on PC named IP_Detector on host to find
out IP addr set by DHCP to target for network connection The
whole Root File System on the target included them all just configured
and run them But
unfortunately unable fully to demo these features on target due to my
sudden
stoke stoped me in doing so Man propose God dispose though!!
Sr R&D Eng FPGA Verilog embeded
Linux x86 [Kontron ]+PowerPC