Hardware Description

Languages : ABEL and Verilog

David Nguyen, Duy-Ky Nguyen, PhD

1. Introduction

ABEL (Advanced Boolean Equation Language) allows you to enter behavior-like descriptions of a logic circuit. ABEL is an industry-standard hardware description language (HDL) that was developed by Data I/O Corporation for programmable logic devices (PLD). We`ll compare with Verilog code

ABEL is really a description language composed of equations, while Verilog tends to be programming language, like C language.

An ABEL Quick Reference CHM file

This brief note presents a very basic ABEL.

2. Basic Structure

A typical template is given below where keywords are in bold and optionals are in bracket [ . . . ].

Comment uses double-quote " or double slash //.

module module_name (
[title string]
[deviceID device deviceType;]
pin declarations 	// pin number is optional, device field should be used if pin number is used
other declarations 	// node as internal signal, for example
equations
equations
[Test_Vectors]
test vectors
end module name

Keyword is case-insensitive, eg module and Module are the same. But user-defined name is case-sensitive, Data and data are different.

3. Data Type

ABEL Verilog
There are 2 data types for combinatory and sequential.
  • istype 'com' (combinatory)
  • istype 'reg' (sequential)
Similar
  • wire (combinatory)
  • reg (sequential)
Logic
  • ^b0, ^b1 (b for binary)
  • ^h12 (h for hex)
  • 34 (decimal)
Logic
  • `b0, `b1
  • `h12
  • 34 or `d12

ABEL and Verilog are similar in data types.

4. Control Statement

if then else is used for state_diagram only, otherwise when then else is used.

5. Operators

OP ABEL Verilog
INV X = !A X = ~A
AND X = A & B X = A & B
OR X = A # B X = A | B
XOR X = A $ B X = A ^ B
XNOR X = A !$ B X = A ~^ B
Group [ D1, D0 ] { D1, D0 }
Range D[7 .. 0] D[7 : 0]
Tri-State 
DOT convention .OE
sig_Z.OE = sig_Z_OE;
sig_Z = sig_Z_val;
	
 ? : 
wire sig_Z = sig_Z_OE ? sig_Z_val : 'hZ;
Mux 
when S == 0 then O = A
else when S == 1 then O = B  
else when S == 2 then O = C
else O = D;
	
 ? : 
wire O = (S==0) ? A : (S==1) ? B : (S==2) ? C : D;  
Flip-Flop 
DOT convention .CLK
sig_Q.CLK = sig_Q_CLK;
sig_Q := sig_Q_val;
	
reg sig_Q;
always @(posedge sig_Q_CLK)	sig_Q <= sig_Q_val;

6. IO Interface

ABEL Verilog
pin for all input, output and inout input, output, inout

ABEL has limitation in clearly stating IO pins !

7. State Diagram

ABEL has async logic in state_diagram block, and sync logic is declared using .CLK. There is only ONE signal name used for both async and sync logic!!!

To convert into Verilog, the signal name is really async signal from state_diagram block. Thuis signal should be postfixed with _D (D for async data) and will be clocked into the original signal name.

7.1. Non-Invert Logic

ABEL code

Q	node	istype	`reg`;
Q.clk = CLK;
state_diagram Q
    state 1 :    if ( cond_1 )    then    0    else    1;
    state 0 :    if ( cond_2 )    then    1    else    0;
Equivalent Verilog 
wire    Q_D = Q ? (cond_1 ? 0 : 1) : cond_2 ? 1 : 0);
always @(posedge CLK)    Q <= Q_D;

7.2. Invert Logic

ABEL code

Q	node	istype	`reg, invert`;
Q.clk = CLK;
state_diagram Q
    state 1 :   if ( cond_1 )   then   0   else   1;
    state 0 :   if ( cond_2 )   then   1   else   0;
Equivalent Verilog code 
wire	Q_D = Q ? (~cond_1) : (cond_2);
always @(posedge CLK)    Q <= ~Q_D;