Projects
Simple Bluetooth for Serial Comm
- Two CSR BT USB dongles have been used on target Microchip PIC32 Eva Kit and TI BeagleBone as BT Server and on host PC (Linux & Win) as BT Client
- Linux libusb and Windows libusb-win32 are too slow to be used for BT server due to time-out, only OS-built BT socket fast enough to do the job
- Raw L2CAP packets are used via HCI ACL packet, NO use of BT profiles. Note that the standard BT serial comm uses SPP profile on RFCOMM protocol
- USB EP_0 is used for output BT Commands, EP_1 for input BT Events, EP_2 for in/out L2CAP packets
BeagleBone Gadget USB : Ethernet over USB and Mass Storage
- Config kernel & Build + Install modules
- Setup host for Ethernet USB
- Setup target for Ether USB
Linux for BeagleBoard project - Part 2
Both BeagleBone Black & White have been coveredSome details on SysV & BusyBox Init in transfer control from kernel to user spaceIn the new version v2, I have NO LUCK with many pre-built root filesystems from many sources : TI, BeagleBone eLinux, ... They all ended up in failures : either not all the way to "bash prompt" or failure in login with many username/passwd found from WWW : (1) root (no psw) (2) username/password. So I had to build a bare minimum filesystem using BuildRoot with additional packages below.
- Flashing : (1) default using GUI dd utility "Win32DiskImager" (2) user-control using "fdisk"
- static full busybox : httpd, telnetd, tftp, ifconfig, … just make symbol link if so required
- ntp : ntpdate (correct clock without using onboard realtime clock)
- samba (3) for Samba Server
- php (CGI) for Server-Side Script : Web Server
- perl : script for pattern extraction, a lot more powerful than using awk or sed
- bash (via make) : script programming
| Original |
New |
|
| U-Boot |
FAT |
FAT |
| Kernel |
Ext2 (Filesystem) |
FAT |
| Update U-Boot & Kernel |
On PC (Copy) |
On Target (over network) |
| Root File-System |
Debian (4- GB) |
BuildRoot (120 MB)
|
Click Here
Linux for FreeScale RIoTboard project
This is my personal project to keep up with eLinux for FreeScale ARM using RIoTboard. There're 2 packages used for evaluation- SVN-2591 with u-boot-2009.08 and linux-3.0.35
- SVN-2777 with u-boot-2013.04 and linux-3.10.17 with device-tree
- Yocto
- BuildRoot
- Debian Wheezy
The limitation of the existing implementation is to use either on-board 4GB flash or external mini SD card for storage. The new implementation uses external micro SD card for storage, it appears better than using mini one where more than half of its size off the board!
The original package has been modified for the following features
- (1) U-boot, (2) kernel and (3) device-tree will be stored as raw binary in the top of un-partitioned flash of 8 MB
- All these 3 images will be updated over network. The existing implementation has u-boot stored as raw binary, but kernel & device-tree stored in FAT and PC tool is used for flashing
- Micro SD will be used as main storage while the existing implement uses mini SD
- NFS boot to support testing kernel , device-tree and drivers
I have used NFS boot to test kernel and filesystem on every
eLinux systems I have worked with and found this board with 1000 BaseT is a lot worse than others with only 100
BaseT. It's the only 1000 BaseT low-cost board I've ever found, very unfortunate! Its schematic reveals there’s no matching impedance between
the network port and the PHY chip.
This causes clock reflection, hence
bad clock quality, resulting in data corruption, therefore so many
re-transmission required : bad performance. It's almsot IMPOSSIBLE to
have successful net boot, I had ONLY ONE, and none for 3 hours, and I
gave up! All network product should pass "EYE TEST", I doubt this board ever had such test!
- SVN server
- Web server
- VSFTPD : file transfer in updating web page
- SSH-Sever : remote maintenance as root
Linux Device Driver in Action
This is my personal project with some in-depth details in writing Linux Device Driver with both read/write to a kernel buffer as FPU, Fake Processor Unit, not Floating-Point;-)- Basic note on several types of memory: offset, logical, physical, virtual, ... brief on MMU (Memory Management Unit)
- A table of driver operations with different correspoding functions in kernel & user space
- Basic types of drivers with both Read & Write operations in different implementations, including Makefile and User App test
- Basic Read & Write
- IOCTL
- Memory Map
- Map Page implementation
- No Page implementation
- Makefile includes
- Load/Unload module
- Test script using "cat & echo" to test read & write ops
- A script detects dynamic major number and makes node accordingly
For a real device, the target FPU_BUF should be pointed to the device base address, say DEV_BASE, then do the followings
- request_region(DEV_BASE,
DEV_SIZE, DEV_NAME) : for multi-user system
- DEV_BUF =
ioremap_nocache(DEV_BASE,
DEV_SIZE) : for
Linux for TI AM18xx SBC8018 project, part 2
This is my personal project with some in-depth details how Linux starts from power-up through bootloader to kernel till full operation
The original Linux ran from NAND flash with a lot of scary error similar to bad sector in hard-drive as it has only ONE FET for ONE storage bit, while regular NOR flash has many. That's why it has more density and cheaper than regular flash.
The board has empty foot-print for SPI flash, so it was populated for a SPI boot to replace NAND boot.
- Details sequential steps from power-up to normal system operation
- Hard boot with internal CPU boot engine to start soft boot u-boot
- u-boot initializes required peripherals to start kernel
- kernel space : kernel initializes all on-board peripherals to start operating system using filesystem transit from kernel to user space
- user space : normal operation
- Customize bootloader u-boot to support SPI with a fresh u-boot tar ball with some extra new env_var to ease Linux debugging via network : update new u-boot itself, kernel, NFS boot
- Configure kernel with a fresh kernel tar ball to make sure it matched with on-board HW device and supprt NFS boot for debugging
- Develop and debug root filesystem from scratch using BuilRoot via NFS boot : /dev, /etc/inittab /etc/init.d/rcS
- Debug filesystem to support Telnet server
- Set up HTTP server
- GPIO Test : LED & Button
- A new char driver
was developped with interrupt
for button and mmap
technique, instead of ioctl, to increase the throughput
- Kernel code was modified to put all LED and buttons fully under new driver
- A user-space test code was written and all button interrupt and
LED worked as expected
Linux for ARM-8 Cortex BeagleBoard project
This is my personal project, so I was solely responsible for it
The best feature of this BeagleBone Board is to boot from SD card with 2 partition (1) FAT for bootloader u-boot & Linux kernel (2) Ext2 for filesystem
- Customize bootloader u-boot with a fresh u-boot tar ball with some extra new env_var to ease Linux debugging via network : update new u-boot itself, kernel, NFS boot
- Configure kernel with a fresh kernel tar ball to make sure it matched with on-board HW device and supprt NFS boot for debugging
- Debugging pre-built filesystem at sys_init point from kernel to user space : inittab, rcS, profile
The existing implementation has
- bootloader (stage-1 MLO and stage-2 uboot.img live in FAT
- Linux kernel and device-tree live in Ext2 in Ext2 filesystem
The new implementation has 4 files (1) MLO (2) uboot.img (3) kernel (4) device-tree all live in FAT. This approach supports to update all those 4 files over network to ease debuuging job during development.
In the end, a BeagleBone Black was set up and run with 128-GB USB drive as a SVN server accessible from outside using feature of port-forwarding in router and free dynamic IP address service from DYNDNS.com.
- The whole Linux SVN server costs under $100 : $55 for board and $35 for USB drive
- There's almost no cost on electric bill to run this server 365/24
Touch-Screen with Barebone Programming project
This is my personal project, so I was solely responsible for it
This project is to investigate if a low-cost capacitive-touch LCD as a user interface @ $ 50
The reference source code was for 8051 with limitation too serious to develop & maintain. So I ported to Atmel AVR with ATMega2560 using WinARM compiler. It has SPI interface to color TFT LCD and I2C to capacitive-touch panel.
Touch-Screen with Android Programming project
This is my personal project, so I was solely responsible for it
This project is to investigate if a low-cost tablet could be used as
a touch-screen user interface. A 8-in tablet Coby Kyros @ $57 has been
used in this project.
http://www.amazon.com/gp/product/B0093XTHJK/ref=oh_aui_detailpage_o01_s00?ie=UTF8&psc=1
A 64bit Android Dev-Kit "adt-bundle-windows-x86_64-20140702.zip" and 64bit Java Dev-Kit-8 have been used in this project.
Linux for ARM-11 project
This is my personal project to keep my e-Linux up to date with new Linux for ARM-11 after working with Linux for x86 and PowerPC on commercial product Time Server, and my personal project for ARM-9
The main limitation of the current Tiny6410 FriendlyARM Linux is its usage of proprietary boot loader called ?superboot? to boot from SD
- Develop bootloader with a u-boot tar ball to replace "superboot". New u-boot has some extra new env_var to ease Linux debugging via network : update new u-boot itself, kernel, NFS boot
- Configure kernel with a fresh kernel tar ball to make sure it matched with on-board HW device and supprt NFS boot for debugging
- Debugging pre-built filesystem at sys_init point from kernel to user space : inittab, rcS, profile
Linux for ARM-9 project, part 1
This is my personal project to keep my e-Linux up to date with new Linux for ARM-9 after working with Linux for x86 and PowerPC on commercial product Time Server, so I was solely responsible for it
- Customize bootloader u-boot with a fresh u-boot tar ball with some extra new env_var to ease Linux debugging via network : update new u-boot itself, kernel, NFS boot
- Configure kernel with a fresh kernel tar ball to make sure it matched with on-board HW device and supprt NFS boot for debugging
- Debugging pre-built filesystem at sys_init point from kernel to user space : inittab, rcS, profile
Pilsner Receiver project
Pilsner Receiver using TI OMAP-L138 with dual-core ARM9 AM1808 and DSP C6748 with TI Code-Composer Studio v.5
My jobs were
- ARM9 AM1808 It's an upgrade version of BlueMoon where it combines receiver, controller (GPS, Oscillator discipline, ...)
- DSP C6748
- Develop DSP bootloader
- Develop new real-time file-system on target TI DSP C6748 to
overcome limitation of TI RTFS
Max file size is 4 GB is about 2 minutes of data measurement while it could go up to 4 hours, ie 120 GB
Maximum of number of open files is 8
Maximum disk size is 120 GB - Develop PC app in C# in access data in newly developed RTFS
- True USB : Bulk & Serial Mode
Successful development of USB stack in bulk-transfer at 360 Mbps (480 max) for Bulk mode and 4 Mbps for Serial mode on target (AM1808)
Successful development of USB app on PC using LibWin32 DotNet in C# for the whole job (PC driver and USB comm) - Develop flexible and secure multi-boot architecture for both FPGA
and MPU
- Boot from selectable multi-image on flash for both ARM & DSP
- Boot from binary download from PC via true USB at 360 Mbps, even faster than using emulator
- Secure field upgrade FPGA image with 2 images : fall-back and operation
Blue-Moon Receiver project
Blue-Moon Receiver using 2 of TI OMAP-L138 with dual-core ARM9 AM1808 and DSP C6748 with TI Code-Composer Studio v.5
My jobs were
- ARM9 AM1808
- Atmel I2C EEPROM AT24C02B
To store calibration data - Maxim I2C Temp Sensor MAX6625PMTT
To monitor unit temp - Winbond SPI Flash W25Q64BVSFIG for FPGA and 2 OMAP binary
images
To store FPGA binary image - Boot loader to separate ARM and DSP binaries
- Field upgrade for both FPGA and OMAP
- Atmel I2C EEPROM AT24C02B
- DSP C6748 using TI PSP driver (Platform Support Package) with DSP
BIOS.5
UPP driver (Universal Parallel Protocol) at rate 123 MByte/s
SATA write for data streaming using TI FAT32 RTFS (Real-Time File-System) - Interprocessor Communication
- SPI between 2 OMAP-L138 : either one could be master to initiate transaction based on interrupt
- Protocol between 2 internal cores ARM & DSP
Simple and effective IPC (Inter-Process Comm) where DSP interrupts ARM, but does polling for ARM request for real-time critical jobs in collecting measuring data from FPGA (UPP bus) and saves to HDD
- PC comm
- Serial Comm with command sequence include in hand-shake for a un-reliable link (like TCP)
- Command sets in target unit
- C# development in both CLI and GUI using MSVS-2010
- Test, Debug & Maintenance
- Field Flash update
Blue-Moon RF Front-End project
Blue-Moon RF as Front-End for Blue-Moon Receiver
My jobs were
- TI SPI 2-channel ADC ADS7230
IF Peak RMS Detector - Maxim SPI 28-port IO Expander MAX7301
- Set Bandwidth
- Set RF Attenuation
- Set IF Attenuation
- Set IF Calibration
- Set IF Detector
Blue-Moon Controller project
Blue-Moon Controller using Atmel ARM7 AT91SAM3S with Code-Sourcery compiler
My jobs were
- FPGA Xilinx XC6SLX9
- Under MCU control via SPI
- Time-stamp for oscillator discipline using GPS PPS from UBlox GPS module
- Provide trigger pulse to 4 receiver to start collecting measuring data
- GPS UBlox using proprietry UBlox binary package for fast transfer
in keeping transfer time far below 1 second
- PPS for oscillator discipline
- Time & Location for marking data measurement in drive-test
- Oscillator discipline
- PC comm
- Serial Comm with command sequence include in hand-shake for a un-reliable link (like TCP)
- Command sets in target unit
- C# development in both CLI and GUI using MSVS-2010
- Test, Debug & Maintenance
- Field Flash update
- Graphic programming in C# using ZedGraph
- Peripherals
- Analog Devices SPI Clock Distribution AD9510
Distribute the main regerence clock 61.44 MHz to Atmel MCU, FPGA, and 4 RF units in differential pairs - Analog Device SPI DAC AD5660
Oscillator discipline - Hittite SPI Fractional PLL HMC830
Provide the fixed main LO freq 375 MHz and variable LO freq 1050 ~ 2460 MHz - Atmel I2C EEPROM AT24C02B
To store calibration data - Maxim I2C Temp Sensor MAX6625PMTT
To monitor unit temp - Winbond FPGA SPI Flash W25Q64BVSFIG
To store FPGA binary image
- Analog Devices SPI Clock Distribution AD9510
FPGA with DSP project
FPGA with DSP using Xilinx Virtex 4 xc4vsx35
My jobs were
- Implement DSP resamplers, correlators and filters using Xilinx DSP cores for I/Q channels from high-speed ADC Analog Devices AD6645 to DSP Analog Devices Tiger-Shark ADSP-TS201
- Verify FPGA simulations to match with Matlab ones
- Develop low-level SW for verification using Analog Device Virtual DSP Compiler of Tiger-Shark ADSP-TS201
Design Summary
--------------
Number of errors: 0
Number of warnings: 14
Logic Utilization:
Number of Slice Flip Flops: 5,814 out of 30,720 18%
Number of 4 input LUTs: 5,754 out of 30,720 18%
Logic Distribution:
Number of occupied Slices: 5,063 out of 15,360 32%
Number of Slices containing only related logic: 5,063 out of 5,063 100%
Number of Slices containing unrelated logic: 0 out of 5,063 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 6,080 out of 30,720 19%
Number used as logic: 3,496
Number used as a route-thru: 326
Number used for Dual Port RAMs: 170
(Two LUTs used per Dual Port RAM)
Number used for 32x1 RAMs: 16
(Two LUTs used per 32x1 RAM)
Number used as Shift registers: 2,072
Number of bonded IOBs: 111 out of 448 24%
IOB Flip Flops: 47
IOB Master Pads: 5
IOB Slave Pads: 5
Number of BUFG/BUFGCTRLs: 7 out of 32 21%
Number used as BUFGs: 7
Number of FIFO16/RAMB16s: 17 out of 192 8%
Number used as FIFO16s: 2
Number used as RAMB16s: 15
Number of DSP48s: 64 out of 192 33%
Number of DCM_ADVs: 2 out of 8 25%
Number of PMCDs: 1 out of 4 25%
Number of BUFRs: 2 out of 24 8%
Number of OSERDESs: 10 out of 448 2%
Number of ICAP_VIRTEX4s: 1 out of 2 50%
Number of STARTUP_VIRTEX4s: 1 out of 1 100%
Number of BUFIOs: 2 out of 32 6%
BlackBriar project
Single Board Compter with Comm Express connector to be used in high-end option for Hydra project
- Memory : SDRAM DDR2 256MB, 8 MB NOR flash for boot loader, kernel, device tree, SPI SD memory card for filesystem
- Misc : PLL ISC570, USB Hub TUSB2046B
- 2 gigaBit Ethernet PHY VSC8211
- PCI-PCIe bridge PLX8112
- Use PLL ICS570 and CPLD to drive all clock from single clock source 25 MHz : 33 MHz for PPC PCI, 125 MHz for gigabit Etjhernet, 100 MHz for PCIe, 48 MHz for USB
- Standard Comm Express connector
- HW
- Board architecture with single clock source to minimize EMI
- Schematic design
- SW : PowerPC Linux
- Freescale Linux 2.6.23 : config kernel, device tree, including modify source code for SPI SD MMC
- Boot loader: config u-boot 1.3.0 to board specific (256MB DDR, .). Use JTAG debugger BDI3000 to load u-boot into blank NOR flash, and u-boot to load itself if so required
- Linux low-level SW driver : I2C EEPROM to store board ID
- Linux filesystem : NFS boot, ext2 filesystem on SD MMC for basic operation : FTPD, HTTPD, Telnetd, .
- Low-level driver and test code to debug, bring up and test prototype in PPC Linux land
- MCU TMS320F28335 with SRAM
- Xilinx FPGA XC3S250E
- UART Comm between MCU and FPGA
- I2C Flash for non-volatile storage
- 12 channels Low Phase Noise outputs
- Standard Comm Express connector
- HW Consulting in TMS320 and FPGA
- SW
- Debug and Bring up prototype/li>
- CPU : FreeScale PowerPC MPC8308 - MAC, PCIe
- Memory : SDRAM DDR2 256MB, 8 MB NOR flash for bootloader, kernel and device tree, 512MB NAND flash for filesystem
- Misc : SPI DAC/OpAmp for 100MHz Oscillator + DDS, I2C RTC (ISL12028), PLL ISC570,
- 1 gigaBit Ethernet PHY VSC8211
- HW
- Consulting architecture : bus protocol (I2C, SPI), SDRAM, flash storage NOR/NAND
- SW : PowerPC Linux
- Freescale Linux 2.6.29.6 : config kernel, device tree
- Boot loader: config u-boot-2009.11-rc1 to board specific (256MB DDR, large-page NAND, .). Use JTAG debugger PEEDI/BDI3000 to load u-boot into blank NOR flash, and u-boot to load itself if so required
- Linux low-level SW driver : config FPGA under Linux control, discipline oscillator via SPI DAC - 100 MHz oscillator
- Linux filesystem stored in NAND flash : NFS boot, JFFS2 filesystem on NAND for basic operation : FTPD, HTTPD, Telnetd, .
- Modify open-source PTPDv2 for this specific HW to testing purpose
- Low-level driver and test code to debug, bring up and test prototype in PPC Linux land
- HW : XC3S400, 100BaseT PHY LXT 971, Kontron X-board
- Verilog RTL
- Ethernet TX / RX frame with
- Calcullate CRC for physical layer (L1/L2) for the PHY chip
- Calculate header and UDP checksum
- Implement protocols : ARP. Ping and NTP
- SW
- Use raw-socket Linux programming for testing
- X86 Linux
- Low-level driver and test code to debug, bring up and test prototype in Linux land, including x86 Linux raw-socket programing
- Discipline oscillator under NTP Time-Stamp
- 80 intructions : arithmetic/logic, branch (interrupt inc), bit/bit-test, data transfer, MCU control (WD inc)
- Use Atmel AVR Studio Assembler to debug instructions and WinAVR C compiler for final test with interrupt
-
CPU : FreeScale PowerPC MPC8313 - MAC, PCI, USB
My jobs were
Hydra project
12-channel Distribution Amplifier with high-end option to include
My jobs were
Norfolk project - Prototype
PTP PCIe card using PTP core in MPC8308
My jobs were
Super-Secure NTP Server project
Super-secure NTP server : responding nothing else but time request
This is my personal project, so I was solely responsible for it
JTAG project
This is my personal project, so I was solely responsible for it
This project investigated a possibility to use JTAG for product quality control.
It was possible to do JTAG programming using FT2232 chip on Windows and bit-bang bit-bang method via parallel port in both Window and Linux platform.
GPS-FPGA Interface project
This is my personal project, so I was solely responsible for it
A MCU has been used to process GPS message to get timing data via UART and store into Dual-Port RAM inside FPGA. This project used only FPGA to extract GPS data without using MCU
This project investigated a possibility to use a FPGA for the job.
Simple FPGA CPU Softcore project(*) using C compiler and supporting interrupt
This is my personal project, so I was solely responsible for it
Big CPU softcore support C compilers, like Altera Nios, Xilinx MicroBlaze. Simple core, like Xilinx PicoBlaze, supports assembly language only, but no interrupts
Design and Implement a softcore supporting C compiler based on Atmel AtTiny RISC archtitecture with about under 100 instructions
The Xilinx XC3S500e eva board was used to the project. It has a LCD, some LEDs, some press button, rotary knob for testing interrupt
XC3S500e
Number of RAMB16s 3 out of 20 15%
Number of Slices 1493 out of 4656 32%
9611B project
Low-cost NIC for WUI (Web User Interface)
- CPU : FreeScale PowerPC MPC8313 - MAC
- Memory : SDRAM DDR2 128MB, 8 MB NOR flash for boot loader, kernel, device tree, 256 MB NAND for filesystem
- Misc : PLL ISC570
- 1 100BaseT Ethernet PTP PHYTER DP83640
My jobs were
- HW
- Board architecture
- Schematic design
- SW : PowerPC Linux
- Freescale Linux 2.6.20 : config kernel, device tree, including modify source code from small-page 32MB to large-page 256MB NAND for filesystem
- Boot loader: config u-boot-1.1.6 to board specific (256MB NAND, .). Use JTAG debugger BDI3000 to load u-boot into blank NOR flasJFFS2 filesystem on NAND for basic operation : FTPD, HTTPD, Telnetd, .
- SW archtitecture for WUI (Smarty, PHP, SQ Lite database)
- Linux Drivers for FPGA & Ethernet Phy DP83640
- Low-level driver and test code to debug, bring up and test prototype in PPC Linux land
- Flash Programming & Product Test
Time Comparator project
Compare time from different sources with GPS time reference
This is my personal project, so I was solely responsible for it
- NTP Server
- PTP Grand Master
- Time Code (IRIG
It involves the following jobs
- HW : Modify XLi platform to support time measurement from
different sources using
- Time Code IRIG option card
- NTP option card
- PTP option card
- FPGA : Design a FPGA to do timestaming 3 different time sources NTP, PTP and IRIG
- SW : VxWorks & x86-Linux
- Modify XLi VxWork to support
- Time-stamps of IRIG, NTP and PTP
- CLI (Command-Line Interface) using serial terminal via PC COMM
- GUI (Graphic User Interface) using keypad and LCD
- Embedded Linux
- WUI (Web User Interface)
- Device drivers
- Discipline oscillator under IRIG, NTP and PTP Time-Stamp
- Modify XLi VxWork to support
Microblaze - uC Linux project
Investigate the possibility in using Xilinx softcore CPU MicroBlaze and uCLinux from PetaLogix. A Xilinx eva board XC3S1600E has been used for this project
This is my personal project, so I was solely responsible for it
- HW-FW :
- config MicroBlaze core with additional simple 32-bit counter
- FPGA image at bottom of the flash
- Boot loader at top of the flash
- SW : Microblaze uC-Linux
- Modify PetaLogix from XC3S500E to XC3S1600E
- uCLinux : web page
- Remote debug
- uC Linux driver
Apollo project
- HW
- MCU AT91SAM7
- GPS module
- FPGA : I2C for remote user inetrface
- SW
- GNU GCC WinARM
- IAR C Compiler
My jobs were FPGA design for an I2C core.
Free RTOS + Atmel AT91SAM7X project
This project investigated the possibility to use an Atmel ARM7 AT91SAM7X with 100-BaseT Ethernet port
This is my personal project, so I was solely responsible for it
An Atmel eva kit AT91SAM7X-EK has been used for this project.
Open-source WinARM Compiler + Free-RTOS was employed in this project to have a simple web page.
Treadstone project PDF
- HW
- MPC8272 + 64MB SDRAM, 64MB flash, PCI
- 2 x 100BaseT PHY DM9161, LXT971
- 2 x USB Hub ISP1105
- Xilinx XC3S1600E : Xilinx Platform flash, SPI flash
- I2C flash
- SW : PowerPC Linux
- Monta Vista Linux kernel 2.6.10
- Boot loader u-boot 1.1.2
- Linux driver for FPGA, I2C, SPI, Ethernet Phy LXT971
- NFS boot
- JFFS2 filesystem
- HW
- Consulting architecture : SDRAM, flash, I2C flash, FPGA and its storage, inc. SPI type
- Debug and bring up prototype
- SW : PowerPC Linux
- Configure kernel
- Config u-boot
- Driver for FPGA, bit-bang I2C flash, bit-bang SPI FPGA flash, direct config FPGA, Ethernet Phy LXT971
- JFFS2 filesystem
- Low-level driver and test code to debug, bring up and test prototype in PPC Linux and HC12 lands
- Production : Flash Programming & Test
- HW
- Kontron X-board SBC
- Xilinx XC3S400
- PCI MAC DP83816
- PHY LXT971
- PCI IF PLX9030
- DAC
- SW
- Monta-Vista Linux kernel 2.4
- HW
- Schematic design
- FPGA design
- SW : x86 Linux
- Config kernel
- Linux PCI driver for FPGA & Network Device NatSemi
- Direct config FPGA under Linux control, instead of using its own flash for fielde upgrade purpose
- Low-level driver and test code to debug, bring up and test prototype in x86 Linux land
- Discipline oscillator under PTP Time-Stamp
- Production : Flash Programming & Test
- HW
- Schematic design
- FPGA to generate time data (second, milli/micro seconds) and time code PTTI on-time with PPS
- Simple UART TX for purpose of debugging and test production
- Encoder output type is required for products, the design went further to include decoder for debugging and testing once in production
- SW
- VxWork on CPU board using Net ARM
- Test code to debug, bring up and test prototype in VxWork land
- Production : Flash Programming & Test
- HW
- HC12
- FPGA processes timing broadcast from CPU over backplane and store into internal DualPort RAM in FPGA with slave SPI for HC12 to get these timing data
- SW
- HC12 Code Warrior
- Low-level driver and test code to debug, bring up and test prototype in HC12 land
- Production : Flash Programming & Test
- HW
- Kontron X-board
- HCS12
- PCI Interface PLX9030
- Xilinx FPGA XC3S400
- PCI MAC DP83816
- 100BaseT PHY LXT971
- DAC + Oscillator
- GPS Module
- SW
- Montavista Linux
- HC12 Code Warrior
- HW
- FPGA Interface to Local Bus of PCI adapter PLX9030
- Debug and Bring up prototype
- SW : x86 Linux
- Config Linux kernel 2.4
- Linux PCI driver for FPGA & Network Device NatSemi
- Basic Linux filesystem to debug HW in Linux land : NFS boot, USB boot and regular boot, DHCP, TFTP, Telnet, .
- Low-level driver and test code to debug, bring up and test prototype in x86 Linux and HC12 lands
- Flash Programming & Product Test
- HW
- NetARM
- FPGA XC2S100
- PHY LXT 971
- DAC + Oscillator
- SW
- VxWork Tornado for NetARM
- Its FPGA was configured by its platform ROM, so it's had no field update feature
- The flash had several images : boot loader, SW application, filesystem. These images were loaded into flash manually and individually. This programmed flash was cloned to make product flash in manufacturing
- Field update feature modify HW board for this feature
- Modify HW board for this feature
- Modify VxWorks SW structure and add new function for this feature
- Flashing in production : create a PERL script to combine all images, including new FPGA image, into a SREC to program a flash from this single file
- Develop flash programming algorithm 60 times faster than existing one
- Production : Flash Programming & Test
- HW
- HC12
- FPGA XC2S50
- DAC
- Opto-coupler
- RS-422
- SW
- HC12 Code Warrior
- HW
- Board design
- FPGA design : parallel bus to backplane, SPI bus to HC12, DPRAM, Time & Frequency measurement
- SW
- Using Code Warrior to write low-level driver and test code to debug, bring up and test prototype
- Production : Flash Programming & Test
- HW : Modify existing TimeCode option to exclude HC12
- FPGA : Develop Verilog code for a Xilinx FPGA XC2S50 to handle both transmit and receive timecode IRIG.
- HW
- NetARM CPU
- GPS ARM7 Chipset GP4020 + RF FrontEnd GP2015
- 100BaseT PHY LXT971
- FPGA XC2100
- DAC + Oscillator
- SW
- VxWork Tornado for NetARM
- MicroTec ARM for GPS ARM
- HW
- Board design
- FPGA design
- SW
- Develop low-level drive and test code in both VxWork and MicroTec to debug, bring-up and test prototype
- SW PLL to discipline oscillator
- Flash Programming & Product Test
- HW
- MC68331
- Async Framer TXC-04228
- Sync Framer NLC-DFIA
- LIU LXT-332
- Altera FPGA EP20K100
- SW
- VxWork MC68331
- VxWork MC860
- Board design
- FPGA design
- Low-level driver and test code to debug, bring-up and test HW using C-compiler for MC68331 and MC860 in Linux environment
- Production : Flash Programming & Test
- HW
- MC68331
- Async Framer TXC-04251
- Sync Framer NLC-DFIA
- LIU LXT-332
- Altera FPGA EPF 10K50
- SW
- VxWork MC68331
- VxWork MC860
- Board design
- FPGA design
- Low-level driver and test code to debug, bring-up and test HW using C-compiler for MC68331 and MC860 in Linux environment
- Production : Flash Programming & Test
- HW
- MC68331
- Async Framer TXC-04251
- Sync Framer NLC-DFIA
- LIU LXT-332
- Altera FPGA EPF 10K50
- SW
- VxWork MC68331
- VxWork MC860
- Board design
- FPGA design
- Low-level driver and test code to debug, bring-up and test HW using C-compiler for MC68331 and MC860 in Linux environment
- Production : Flash Programming & Test
- HW
- MC68331
- Async Framer TXC-04251
- Sync Framer NLC-DFIA
- LIU LXT-332
- Altera FPGA EPF 10K50
- SW
- VxWork MC68331
- VxWork MC860
- Board design
- FPGA design
- Low-level driver and test code to debug, bring-up and test HW using C-compiler for MC68331 and MC860 in Linux environment
- Production : Flash Programming & Test
- HW
- MC68331
- Sync Framer NLC-DFIA
- LIU LXT-332
- Xilinx FPGA XC4036
- SW
- VxWork MC68331
- VxWork MC860
- Board design
- FPGA design
- Low-level driver and test code to debug, bring-up and test HW using C-compiler for MC68331 and MC860 in Linux environment
- Production : Flash Programming & Test
- to combine several images into a single one from both Intel HEX and Motorala SREC format as it's more reliable and more productive to combine into only 1 file.
- to deal with big and little endian
This project investigated a possibility to use Linux OS for a PowerPC MPC8272
My jobs were
Tahiti project PDF : IEEE-1588 PTP PDF
This project was for a IEEE-1588 PTP master/slave PTP and opened the whole new business for Symmytricom as a pioneer in this area.
My jobs were was
Moorea project
This project updated old products for cost reduction as old/obsolete parts were getting more and more expensive over time. This project involved 6 boards (CPU, Serial T1/E1, PTTI, Para-BCD, Osc, F10M Distr). The plan was to add 2 contractor to complete the project. I insisted I could handle myself alone. The following plan was to add one contractor. I also guarantee myself could handle quite convenient. I completed the project in less than 6 months
My jobs were board and FPGA design, low-level SW to debug and bring up all boards using Lauterbach debugger, improve SW PLL algorithm to improve clock quality (Alan deviation) using PID, Fuzzy Logic and Kalman filter
This project was a huge success and beyond expectation in terms of both design specs and HW/SW partition and production test support with built-in test feature with using external test equipments like PTTI time-code or para-BCD reader, actually impossible to find nowadays
Have Quick project
This project was to create an option card for XLi platform to generate HaveQuick timecode used in US military.
My jobs were board and FPGA designs, low-level SW to config FPGA to debug and bring up the prototype.
Quick-Silver project
This project investigated a possibility to use SBC and Linux for future products, including FPGA design methodolofy using Verilog
My jobs were
This project had a huge success as it was used for very successful products Tahiti and Sync Server
>> BackPlane
Oscillator Discipline using Kalman Filter
Kalman filter is based on 2 system variances (1) system modeling uncertainty Q (2) output measurement accuracy R. Kalman filter is proved mathematically that there exist Q & R such that the impact of noise/uncertainty on the system is minimal. But there`s no analytical calculation of such Q & R, somehow we must find their intial values to start with, then do fine-tuning using "trial-and error" approach to see if the performance is better than classical PID controller.
My job was to implement a Kalman Filter to discipline oscillator on XLi product for product quality improvement.
Oscillator
discipline is composed of 2 phases (1) Frequency Lock Loop (FLL) and
(2) Phase Lock Loop (PLL). Due to system dynamics, PLL is active when
output is greater than 1e-8 (10 nanosecond), so start with R=1e-16
(variance is square of deviation). It's arbitrarily to start with Q = R
A wide range of Q&R around the initial value 1e-16 were attempted and Kalman filter and PID appear similar performance. It's probably because the system has no uncertainty high enough for Kalman to show its best ?
The Original Kalman Filter paper is here
My Kalman Filter PDF file is here
Upgrade XLi project
This project was to upgrade an existing Network Time Server product with new features
The exisiting Xli product had some limitations
My jobs were to develop a field update feature for FPGA image over network and develop a procedure for flashing from a file, rather than cloning
FTM project PDF
This project to update an old product for cost reduction
My jobs were
Using opto-coupler instead of transformer for isolation, reduced cost from $75 to $3 when replacing new isolation amplifier; it passed UL compliant
TimeCode FPGA
A micro-controller interrupt-based HC12 used with a FPGA to handle time-code IRIG in existing product.
The HC12-based option was working fine with regular IRIG-B at 1 KHz, but in doublt with IRIG-G at 1 MHz. This project was to used only FPGA for the job
The performance was better than HC12-based option due to interrupt latency.
It was working fine with IRIG-G at 1 MHz carrier frequency.
Columbia project PDF
This project was to upgrade old Network Time Server
My jobs were
ES24D1 project PDF
Expansion Shelf 24 Async/Sync DS1 Unit
My jobs were
S3D1 project PDF
USAM DS1 Unit
My jobs were
D1TIU project
My jobs were
BNUDS1 project
My jobs were
H24D1 project
High-Density DS1 Unit
My jobs were
Production Test Support project(*)
I was solely responsible for this project
Setup production test environment to use all our test code in testing all our products in both Linux and Window environments. This was also used for other products.
Set up flashing procedures in production for both Intel HEX and Motorola SREC
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